Figure 8-9 Failover Logic Overview - Emerson ATCA-8310 Manual

Figure 8-9
ENABLE ( PWRGD )
ACTIVE
REQ _ CNTR
HEALTH _ O
HEALTH _ I
8.2.3.12.1 External failure input signals
Status register (write one to clear)
Interrupt mask register
Failover mask register
Active level control (active-high/low)
Edge/level control (fault signal is level- or edge triggered)
"Healthy" signals from other FPGA devices (DMC base, DMC 1, DMC 2 and ARTM) which
contain the same logic for driving their healthy signals.
ATCA-8310 Installation and Use (6806800M72D)
Failover Logic Overview
Blade 1
FPGA
R Q
NEG _ O
S
R / S
NEG _ I
Backplane
FPGA
NEG _ O
NEG _ I
CPLD and FPGA
Blade 2
ENABLE ( PWRGD )
ACTIVE
REQ _ CNTR
Q R
S
R / S
HEALTH _ O
HEALTH _ I
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