Super Io Module; Gpp Reset Controller - Emerson ATCA-8310 Manual

CPLD and FPGA
8.2.3.3

Super IO Module

The Super IO consists of two serial devices COM1 and COM2 connected via the LPC bus
interface. The Super IO has the following features:
Serial IRQ interface compatible with serialized IRQ support for LPC systems
Two fully functional Serial ports COM1and COM2 compatible to 16550C
Configurable I/O addresses and interrupts
Configurable Pre-divider to support 48 MHz CLK_UART clock input
8.2.3.4

GPP Reset Controller

8.2.3.4.1 GPP XDP Debugger Reset
For debugging the XDP CPU debugger must be able to reset the board.
When PWR_GOOD is high and the reset signal GPP_XDP_DBR_ is asserted the reset signal
GPP_SYS_RST_ is driven low.
8.2.3.4.2 GPP Platform Reset
The GPP Platform Reset is asserted in the following cases:
Face Plate Push Button reset or ARMT Push Button reset.
SPP holds the GPP in reset
The GPP should stay in reset until reset source is released. A GPP reset is triggered by a falling
edge of GPP_SYS_RST_. GPP starts reboot even GPP_SYS_RST_ is still asserted. Therefore a
state machine is needed to keep the system in reset until the reset source is released.
The PCH signal GPP_SYS_RST_ is used to trigger a Cold Reset. The PCH has a 16 ms debounce
filter for the GPP_SYS_RST_ signal. Therefore the low and high states need to be stable for at
least 16 ms.
GPP_SYS_RST_ is edge sensitive. A high to low transition (after debounce time) triggers a cold
reset. The PCH asserts for 5 to 6 ms the platform reset signal GPP_PLTRST_. The reset may be
delayed depending on some system states.
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ATCA-8310 Installation and Use (6806800M72D)