Asynchronous Receiver Transmitter; Figure 8-5 Telecom Clock Block Diagram - Emerson ATCA-8310 Manual

Figure 8-5
CLK2A
CLK2B
CLK1A
CLK1B
CLK3A
CLK3B
8.2.3.2

Asynchronous Receiver Transmitter

Glue FPGA incorporates two Texas Instruments-compatible TL16C550C asynchronous
communications elements (COM 1 and COM 2) with Auto-Flow control. These UART units may
be mapped via Super IO Module.
For details on the address and interrupt map of the UART units via Super IO see
Configuration Registers on page
ATCA-8310 Installation and Use (6806800M72D)
Telecom Clock Block diagram
6.48MHz
Glue Logic FPGA
SYNC_2
EN_CLK3
EN_CLK3
272.
CPLD and FPGA
I12
ACS
I13 8520B
I7
I8
Sync2K
I10
I9
I14 (T3
BITS)
REFCLK1
REFCLK2
Logical Device
353