Table 8-93 Gpp Remote Interrupt Status Register; Table 8-94 Gpp Other Interrupt Status Register - Emerson ATCA-8310 Manual

CPLD and FPGA
8.2.2.3.18 GPP Interrupt Registers
GPP Interrupt Status Registers

Table 8-93 GPP Remote Interrupt Status Register

Address: 0x20 - 0x21
Bit Interrupt Name
0 REMOTE_RESET_A
1 REMOTE_RESET_D
2 REMOTE_WD_HALF
3 REMOTE_WD_RESET
7:4 MAILBOX[4:1]
11:8 SEMAPHORE[4:1]
15:12 -

Table 8-94 GPP Other Interrupt Status Register

Address: 0x22
Bit Interrupt Name
0 WD_HALF
1 GPP_PROCHOT
2 GPP_DIMM0
3 GPP_DIMM1
4 ROLE_CHANGE
5 HEALTHY_O_D
6 HEALTHY_I_D
7 HEALTHY_I_A
GPP Interrupt Mask and Map Registers
Each GPP interrupt signal of the
312
Description
Remote CPU Reset asserted (SPP)
Remote CPU Reset deasserted (SPP)
Remote CPU Watchdog half expired
(SPP)
Remote CPU Watchdog expired. SPP
watchdog reset
SPP Mailbox 1 to 4 written.
SPP Semaphore 1 to 4 released.
Reserved
Description
Watchdog half expired
GPP Processor Hot
GPP DIMM thermal event 0
GPP DIMM thermal event 1
Role Change
Local Healthy deasserted
Remote Healthy deasserted
Remote Healthy asserted
GPP Remote Interrupt Status Register
ATCA-8310 Installation and Use (6806800M72D)
Default Access
0 GPP: r/w1c
0 GPP: r/w1c
0 GPP: r/w1c
0 GPP: r/w1c
0 GPP: r/w1c
0 GPP: r/w1c
0 r
Default Access
0 GPP: r/w1c
0 GPP: r/w1c
0 GPP: r/w1c
0 GPP: r/w1c
0 GPP: r/w1c
0 GPP: r/w1c
0 GPP: r/w1c
0 GPP: r/w1c
can be mapped to any IRQ