Figure 7-1 Ipmc/Mmc Block Diagram Of The Atca-8310 - Emerson ATCA-8310 Manual

Registers within the Glue Logic FPGA and the Power CPLD can be accessed by the IPMC via SPI
bus. This enhances the capabilities of the IPMC. The Glue Logic FPGA can be used to monitor
the CPU status, the Payload reset cause, the port80 BIOS post codes and to control the boot
bank selection of the Intel CPU. The Power CPLD controls the enabling and monitoring of power
good signals from all on-board power converters.
A functional block diagram of the ATCA-8310 IPMC/MMC system is shown in the following
figure:
Figure 7-1
DSP Module
DMC Module
DMC Module
Temperature
Temperature
Sensor
Sensor
Temperature
Sensor
FRU Information
FRU Information
FRU Information
Presence Sensor
Presence Sensor
Presence Sensor
Power Interface
Sensors
Temperature
Sensors
ATCA-8310 FRU
Information
Voltage Sensors
System Event Log
(SEL)
ATCA-8310 Installation and Use (6806800M72D)
Intelligent Peripheral Management Controller
IPMC/MMC block diagram of the ATCA-8310
P4080
Glue Logic FPGA
Renesas H8S
2166 (IPMC)
2
I C
WDT
b
u
f
f
e
r
Power
CPLD
ATMEGA 128
(MMC at RTM)
IPMB-L
WDT
b
u
f
f
e
r
IPMB-0
Mezzanine Card
Presence Sensor
Temperature Sensor
FRU Information
SFP Presence
Sensors
Temperature
2
I C
Sensors
ATCA-8310 FRU
Information
Voltage Sensors
203