Table 8-12 Power-Up Failure Codes Part 1 Register; Table 8-13 Power-Up Failure Codes Part 2 Register - Emerson ATCA-8310 Manual

CPLD and FPGA
8.1.2.2.5 Power-up Failure Codes Registers
The cause of Power-up sequence failures or Power fails during payload running are accessible
by the IPMC via SPI Bus. The Power-Up Failure Codes Registers is latched status while failing.
When the IPMC repower the board, the registers are set to the default values.

Table 8-12 Power-up Failure Codes Part 1 Register

CPLD Address: 0x8
Bit Description
3:0 Latched State when Power fail occurs.
0: No Error
Other: The number corresponds to the Power state machine encoding.
7:3 Reserved

Table 8-13 Power-up Failure Codes Part 2 Register

CPLD Address: 0x9
Bit Description
0 12V Power Good failed. Last inverted Level PWRGD_VP12
1 5V Power Good failed. Last inverted Level PWRGD_VP5
2 3.3V Power Good failed. Last L inverted Level PWRGD_V3P3
3 2.5V Power Good failed. Last inverted Level PWRGD_V2P5
4 1.8V Power Good failed. Last inverted Level PWRGD_V1P8
5 1.2V Power Good failed. Last inverted Level PWRGD_V1P2
6 1.2V Power Good Ethernet failed. Last inverted Level PWRGD_V1P2
Ethernet
7 1.0V Power Good failed. Last inverted Level PWRGD_V1P0
252
Default
0
0
Default
0
0
0
0
0
0
0
0
ATCA-8310 Installation and Use (6806800M72D)
Access
SPI: r
r
Access
SPI: r
SPI: r
SPI: r
SPI: r
SPI: r
SPI: r
SPI: r
SPI: r