Table 8-164 Dmc 2 Spi Ls Word Data Register; Table 8-165 Dmc 2 Spi Ms Word Data Register; Table 8-166 Artm Spi Access Control Register - Emerson ATCA-8310 Manual

Table 8-164 DMC 2 SPI LS Word Data Register

Address: 0xCA - 0xCB
Bit Description
15:0 DMC 2 SPI LS Word Write Data Register.
Contains the write bits 15:0 for a DMC register write access
DMC 2 SPI LS Word Read Data Register.
Contains the data bits 15:0 of the selected DMC 32 bit register
when the DMC SPI access has terminated successfully.
Note: Read DMC 2 SPI LS Word Data Register content as long SPI
access not started.

Table 8-165 DMC 2 SPI MS Word Data Register

Address: 0xCC -0xCD
Bit Description
15:0 DMC 2 SPI MS Word Write Data Register.
Contains the write bits 31:16 for a DMC register write access
DMC 2 SPI MS Word Read Data Register.
Contains the data bits 31:16 of the selected DMC 32 bit register
when the DMC SPI access has terminated successfully.
Note: Read DMC 2 SPI MS Word Data Register content as long SPI
access not started.
8.2.2.3.40 ARTM SPI Access Registers

Table 8-166 ARTM SPI Access Control Register

Address: 0xD0
Bit Description
5:0 ARTM SPI Address. (up to 64 bytes)
6 SPI Busy Bit:
0: Ready for next read or write access
1: Busy. The SPI clock is still toggling.
ATCA-8310 Installation and Use (6806800M72D)
CPLD and FPGA
Default Access
- SPP: w
0 SPP: r
Default Access
- SPP: w
0 SPP: r
Default Access
0 SPP: r/w
0 SPP: r
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