Table 8-58 Modem Control Register (Mcr) - Emerson ATCA-8310 Manual

CPLD and FPGA
This 8-bit register controls the interface with the modem or data set (or a peripheral device
emulating a modem).

Table 8-58 Modem Control Register (MCR)

IO Address: Base + 4
Bit
Description
0 Data terminal ready (DTR#) output control:
1: DTR# output in low (active) state
0: DTR# output in high state
1 Request to send (RTS#) output control:
1: RTS# output in low (active) state
0: RTS# output in high state
2 User output control signal (OUT1#):
1: OUT1# output in high state
0: OUT1# output in low state
Not supported
3 User output control signal (OUT2#):
1: OUT2# output in high state
0: OUT2# output in low state
Not supported
4 Local loop back diagnostic control
When loop back is activated: Transmitter TXD is set high. Receiver
RXD is disconnected. Output of Transmitter Shift register is looped
back into the receiver shift register input. Modem control inputs
are disconnected Modem control outputs are internally connected
to modem control inputs. Modem control outputs are forced to
the inactive (high) levels:
1: Loop back mode activated
0: Normal operation
5 Autoflow control enable (AFE):
1: Autoflow control enabled (auto-RTS# and auto-CTS# or auto-
CTS# only enabled)
0: Autoflow control disabled
7:6 Reserved
284
Default
0
0
0
0
0
0
0
ATCA-8310 Installation and Use (6806800M72D)
Access
GPP: r/w
GPP: r/w
GPP: r/w
GPP: r/w
GPP: r/w
GPP: r/w
r