Table 8-37 Super Io Device Revision Register; Table 8-38 Super Io Lpc Control Register; Table 8-39 Global Super Io Serirq And Pre-Divide Control Register - Emerson ATCA-8310 Manual

Table 8-37 Super IO Device Revision Register

Index Address: 0x21
Bit
7:0

Table 8-38 Super IO LPC Control Register

Index Address: 0x28
Bit
0
7:1

Table 8-39 Global Super IO SERIRQ and Pre-divide Control Register

Index Address: 0x29
Bit
0
1
3:2
7:4
ATCA-8310 Installation and Use (6806800M72D)
Description
Device Revision
Description
LPC Bus Wait States:
1: Long wait states (sync 6)
Reserved
Description
SERIRQ enable:
0: disabled. Serial interrupts disabled.
1: enabled. Logical devices participate in
interrupt generations.
SERIRQ Mode:
1: Continuous Mode
UART Clock pre-divide for COM1 and COM2
00: divide by 1
01: divide by 8
10: divide by 26 (CLK_UART is 48 MHz)
11: reserved
Reserved
CPLD and FPGA
Default Access
0x01 GPP: r
Default Access
1 GPP: r
0 GPP: r
Default Access
0 GPP: r/w
1 GPP: r
0 GPP: r/w
0 r
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