Emerson ATCA-8310 Manual page 335

Table 8-141 Cascade Interrupt Enable Register (continued)
Address: 0x94 - 0x95
Bit Interrupt Signal
1 DMC_HOUT_DSP_
2 DMC_PWRGD
3 -
4 DMC1_CONF_CRC_ERR
5 DMC1_HOUT_DSP_
6 DMC1_PWRGD
7 -
8 DMC2_CONF_CRC_ERR
9 DMC2_HOUT_DSP_
10 DMC2_PWRGD
11 -
15:12 -
ATCA-8310 Installation and Use (6806800M72D)
Description
DMC Base signals host interrupt
enable.
0: Disabled
1:Enabled
DMC Base power good fail enable.
0: Disabled
1:Enabled
Reserved
DMC 1 signals a critical error enable.
0: Disabled
1:Enabled
DMC 1 signals host interrupt enable.
0: Disabled
1:Enabled
DMC 1 power good fail enable.
0: Disabled
1:Enabled
Reserved
DMC 2 signals a critical error enable.
0: Disabled
1:Enabled
DMC 2 signals host interrupt enable.
0: Disabled
1:Enabled
DMC 2 power good fail enable.
0: Disabled
1:Enabled
Reserved
Reserved for ARMT
CPLD and FPGA
Default Access
0 SPP: r/w
0 SPP: r/w
0 r
0 SPP: r/w
0 SPP: r/w
0 SPP: r/w
0 r
0 SPP: r/w
0 SPP: r/w
0 SPP: r/w
0 r
0 r
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