Table 8-49 Gpp Uart Register Overview - Emerson ATCA-8310 Manual

CPLD and FPGA
The state of the Divisor Latch Bit (DLAB), which is the MOST significant bit of the Serial Line
Control Register (SCR), affects the selection of certain of the UART registers. The DLAB bit must
be set high by the system software to access the Baud Rate Generator Divisor Latches (DLL and
DLM).

Table 8-49 GPP UART Register Overview

LPC IO Address
Base
Base
Base + 1
Base + 2
Base + 2
Base + 3
Base + 4
Base + 5
Base + 6
Base + 7
Base
Base + 1
GPP UART Registers DLAB=0
- Receiver Buffer Register (RBR)
276
DLAB Bit value Description
0 Receiver Buffer (RBR). Read Only
0 Transmitter Holding (THR). Write Only.
0 Interrupt Enable Register (IER)
X Interrupt Identification Register (IIR). Read Only
X FIFO Control Register (FCR). Write Only.
X Line Control Register (LCR)
X Modem Control Register (MCR)
X Line Status Register (LSR). Read Only
X Modem Status Register (MSR). Read Only
X Scratch Pad Register (SCR).
1 Divisor Latch LSB (DLL)
1 Divisor Latch MSB (DLM)
ATCA-8310 Installation and Use (6806800M72D)