Table 8-201 Dsp Reset Status Register; Table 8-202 Dsp Watchdog Interrupt Status Register - Emerson ATCA-8310 Manual

CPLD and FPGA
This register monitors the Reset status of 10 DSPs.

Table 8-201 DSP Reset Status Register

Bit Acronym
15...10 -
9 DspRes9
8 DspRes8
7 DspRes7
6 DspRes6
5 DspRes5
4 DspRes4
3 DspRes3
2 DspRes2
1 DspRes1
0 DspRes0
8.4.2.7.3 DSP Watchdog Interrupt Status Register
Address: 0xA4, DspWdgStaReg
Width: 16 bit
This register monitors the Watchdog Interrupt status of 10 DSPs. If a Watchdog Interrupt
occurs, the respective bit is set. It can be reset by writing the respective bit in
DspWdgStaResReg.

Table 8-202 DSP Watchdog Interrupt Status Register

Bit
15...10
9
8
408
Type Description
- reserved
R 0b1: DspRes9, active if DSP9 is in reset
R 0b1: DspRes8, active if DSP8 is in reset
R 0b1: DspRes7, active if DSP7 is in reset
R 0b1: DspRes6, active if DSP6 is in reset
R 0b1: DspRes5, active if DSP5 is in reset
R 0b1: DspRes4, active if DSP4 is in reset
R 0b1: DspRes3, active if DSP3 is in reset
R 0b1: DspRes2, active if DSP2 is in reset
R 0b1: DspRes1, active if DSP1 is in reset
R 0b1: DspRes0, active if DSP0 is in reset
Acronym Type Description
- - reserved
DspWdg9 R 0b1: DspWdg9, active if DSP9 Watchdog
Timer has expired
DspWdg8 R 0b1: DspWdg8, active if DSP8 Watchdog
Timer has expired
Default
undef
0b0
0b0
0b0
0b0
0b0
0b0
0b0
0b0
0b0
0b0
Default
undef
0b0
0b0
ATCA-8310 Installation and Use (6806800M72D)
Pwr Soft
- -
F F
F F
F F
F F
F F
F F
F F
F F
F F
F F
Pwr Soft
- -
F F
F F