Table 8-158 Dmc Base Spi Ls Word Data Register; Table 8-159 Dmc Base Spi Ms Word Data Register; Table 8-160 Dmc 1 Spi Control Register - Emerson ATCA-8310 Manual

CPLD and FPGA

Table 8-158 DMC Base SPI LS Word Data Register

Address: 0xBA -0xBB
Bit Description
15:0 DMC Base SPI LS Word Write Data Register.
Contains the write bits 15:0 for a DMC register write access
DMC Base SPI LS Word Read Data Register.
Contains the data bits 15:0 of the selected DMC 32 bit register
when the DMC SPI access has terminated successfully.
Note: Read DMC Base SPI LS Word Data Register content as long SPI
access not started.

Table 8-159 DMC Base SPI MS Word Data Register

Address: 0xBC -0xBD
Bit Description
15:0 DMC Base SPI MS Word Write Data Register.
Contains the write bits 31:16 for a DMC register write access
DMC Base SPI MS Word Read Data Register.
Contains the data bits 31:16 of the selected DMC 32 bit register
when the DMC SPI access has terminated successfully.
Note: Read DMC Base SPI MS Word Data Register content as long
SPI access not started.
8.2.2.3.38 DMC 1 SPI Access Registers
A write access to the DMC 1 SPI Control Register start the corresponding SPI access.

Table 8-160 DMC 1 SPI Control Register

Address: 0xC0 -0xC1
Bit Description
1:0 Reserved
7:2 DMC 1 address. Selects a 32 bit DMC register.
11:8 DMC 1 Byte Select. When the corresponding select bit is set the
corresponding byte of the selected DMC register can be accessed.
346
Default
-
0
Default
-
0
Default
0
0
0
ATCA-8310 Installation and Use (6806800M72D)
Access
SPP: w
SPP: r
Access
SPP: w
SPP: r
Access
r
SPP: r/w
SPP: r/w