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Video Input Interface Pin Assignment
Part 4.6: Gigabit Ethernet Interface
The
FPGA
communication services through the Realtek RTL8211EG Ethernet PHY chip.
The RTL8211EG chip supports 10/100/1000 Mbps network transmission rate
and communicates with the FPGA through the GMII interface. RTL8211EG
supports MDI/MDX adaptive, various speed adaptations, Master/Slave
adaptation, and support for MDIO bus for PHY register management.
The RTL8211EG will detect the level status of some specific IOs to
determine their working mode after powered on. Table 4-6-1 describes the
default setup information after the GPHY chip is powered on.
Configuration Pin
PHYAD[2:0]
SELRGV
AN[1:0]
RX Delay
TX Delay
Mode
38 / 54
FPGA Video Processing Development Platform AV6045 User Manual
Pin Name
2867_CLKP
2867_CLKN
2867_D[0]
2867_D[1]
2867_D[2]
2867_D[3]
2867_D[4]
2867_D[5]
2867_D[6]
2867_D[7]
development
Instructions
MDIO/MDC Mode PHY Address
3.3V, 2.5V, 1.5/1.8V voltage selection
Auto-negotiation configuration
RX clock 2ns delay
TX clock 2ns delay
RGMII or GMII selection
Table 4-6-1: PHY chip default configuration value
Contact Email: rachel.zhou@alinx.com.cn
board
provides
FPGA Pin
C11
A11
A3
C5
A4
A5
D6
B6
C6
A6
users
with
Configuration value
PHY Address 011
3.3V
(10/100/1000M) adaptive
Delay
Delay
RGMII
network
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