Xilinx AV6045 User Manual page 40

Figure 4-6-2: Gigabit Ethernet interface on the Carrier board
Gigabit Ethernet pin assignments：
Pin Name
E_GCLK
E_TXD0
E_TXD1
E_TXD2
E_TXD3
E_TXEN
E_TXC
E_RXC
E_RXDV
E_RXD0
E_RXD1
E_RXD2
E_RXD3
E_CRS
E_RESET
E_MDC
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FPGA Video Processing Development Platform AV6045 User Manual
FPGA Pin
D20
H18
G22
H21
H22
M20
H20
D19
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K19 RGMII transmit clock
E20
E22
F21
Transmit enable signal
RGMII Receive Clock
K21 Receive data valid signal
J20
L19
Carrier Sense Signal
J19 MIMO Management Clock
Description
Transmit Data bit0
Transmit Data bit1
Transmit Data bit2
Transmit Data bit3
MII Transmit Clock
Receive Data Bit0
Receive Data Bit1
Receive Data Bit2
Receive Data Bit3
Reset Signal