Part 3.1: Ac6045 Core Board Introduction; Part 3.2: Ddr3 Dram - Xilinx AV6045 User Manual

Part 3.1: AC6045 Core Board Introduction

FPGA+ DDR3 core board is based on XILINX's SPARTAN6 series
XC6SLX45-2FG484I. This chip develops a high-performance core board with
high speed, high bandwidth and high capacity. It is suitable for video image
processing and high-speed data acquisition.
This core board uses MICRON's MT41J128M16LA-187E DDR3 chip with
a capacity of 2Gbit; 16bit bus mode, read and write data bandwidth between
FPGA and DDR3 is up to 10Gb; this configuration can meet the needs of 4
channels of 1080p video processing.
This core board expands 172 IO ports, which is a good choice for users
who need a lot of IO. Moreover, the FPGA chip to the interface is treated with
the same length, and the core board size is only 60*60 (mm), which is very
suitable for secondary development.

Part 3.2: DDR3 DRAM

Figure 3-2-1 detailed part of the DDR3 schematic (For details, please refer
to the schematic provided by us.)
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FPGA Video Processing Development Platform AV6045 User Manual
Figure 3-2-1: DDR3 schematic
Contact Email: rachel.zhou@alinx.com.cn