Xilinx AV6045 User Manual page 14

FPGA Video Processing Development Platform AV6045 User Manual
In addition, the normal operation of DDR3 requires DDR3 address line and
control line to provide termination voltage VTT and DDR3 chip reference
voltage VREF, VTT and VREF voltage are both 1.5V, the following Figure 3-2-1
is the power part schematic.
Figure 3-2-2: DDR3 Power for VTT/VREF
Figure 3-2-3: DDR3 Power Circuit on the FPGA Board
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