Xilinx AV6045 User Manual page 39

FPGA Video Processing Development Platform AV6045 User Manual
When the network is connected to Gigabit Ethernet, the data
transmission of FPGA and PHY chip RTL8211EG is communicated through the
RGMII bus, the transmission clock is 125Mhz. The receive clock E_RXC is
provided by the PHY chip, the transmit clock E_GTXC is provided by the FPGA,
and the data is sampled on the rising edge of the clock.
When the network is connected to 100M Ethernet, the data transmission of
FPGA and PHY chip RTL8211EG is communicated through the GMII bus, the
transmission clock is 25Mhz. The receive clock E_RXC is provided by the PHY
chip, the transmit clock E_GTXC is provided by the FPGA, and the data is
sampled on the rising edge of the clock.
Figure 4-6-1: Gigabit Ethernet Interface Schematic
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