Part 6.3: Gigabit Ethernet Interface - Alinx ZYNQ7000 FPGA User Manual

ZYNQ FPGA Development Board AC7010/AC7020 User Manual
DDR3_CKE

Part 6.3: Gigabit Ethernet Interface

The AC7010/AC7020 FPGA core board provides network communication
services to users through Micrel's KSZ9031RNX Ethernet PHY chip. The
Ethernet PHY chip is connected to the GPIO interface of the PSNK 501 of the
ZYNQ. The KSZ9031RNX chip supports 10/100/1000 Mbps network
transmission rate and communicates with the MAC layer of the Zynq7000 PS
system through the RGMII interface. KSZ9031RNX supports MDI/MDX
adaptation, various speed self-adjustment, Master/Slave adaptation, and
supports MDIO bus for PHY register management. The KSZ9031RNX
power-on will detect the level status of some specific IOs to determine their
working mode.
Table 6-2 describes the default setup information after the GPHY chip is
powered up.
Configuration Pin
PHYAD[2:0]
CLK125_EN
LED_MODE
MODE0~MODE3
When the network is connected to Gigabit Ethernet, the data
transmission of ZYNQ and PHY chip KSZ9031RNX is communicated through
the RGMII bus, the transmission clock is 125Mhz, and the data is sampled on
the rising edge and falling samples of the clock.
When the network is connected to 100M Ethernet, the data transmission of
ZYNQ and PHY chip KSZ9031RNX is communicated through RMII bus, and
the transmission clock is 25Mhz. Data is sampled on the rising edge and falling
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PS_DDR_CKE_502
Instructions
MDIO/MDC Mode PHY Address
Enable 125Mhz clock output
selection
LED mode configuration
Link adaptation and full duplex
configuration
Table 6-2: PHY chip default configuration value
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N3
Configuration value
PHY Address is 001
Enable
Single LED mode
10/100/1000 adaptive, compatible
with full-duplex, half-duplex