Part 5: Clock Configuration; Part 5.1: Ps System Clock Source - Alinx ZYNQ7000 FPGA User Manual

ZYNQ FPGA Development Board AC7010/AC7020 User Manual
mode. After the ZYNQ7000 chip is powered up, it will detect the level of the
responding MIO port to determine which startup mode. Users can select
different startup modes through the J13 jumper on the FPGA development
board. The J13 startup mode configuration is shown in Table 4-1.

Part 5: Clock Configuration

The AC7010/AC7020 core board provides an active clock for the PS
system, and the clock of the PL logic part can be generated by the PLL of the
PS part. Alternatively, the 50Mhz crystal oscillator can be used to provide a
clock source to achieve separate operation of the PS system and PL logic.

Part 5.1: PS system clock source

The ZYNQ chip provides a 33.333MHz clock input to the PS section via
the X1 crystal on the FPGA core board. The input of the clock is connected to
the pin of the PS_CLK_500 of the BANK500 of the ZYNQ chip. The schematic
diagram is shown in Figure 5-1:
Figure 5-1: Active crystal oscillator to the PS section
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J13
Connect the left two pins
Connect the middle two pins
Two pins connected to the right
Table 4-1: J13 startup mode configuration
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Jump cap position Start mode
SD Card
QSPI FLASH
JTAG