Part 6.2: Ddr3 Dram - Alinx ZYNQ7000 FPGA User Manual

ZYNQ FPGA Development Board AC7010/AC7020 User Manual
Configure chip pin assignments:
Signal Name
QSPI_SCK
QSPI_CS
QSPI_D0
QSPI_D1
QSPI_D2
QSPI_D3

Part 6.2: DDR3 DRAM

The AC7010 FPGA core board is equipped with two SKHynix 2Gbit DDR3
chips (total 4Gbit),
MT41J128M16HA-125). The AC7020 FPGA core board is equipped with two
SKHynix 4Gbit DDR3 chips (total 8Gbit), model H5TQ4G63AFR-PBI
(compatible with MT41J256M16RE-125).
The bus width of DDR is 32bits in total, and the maximum operating speed
of DDR3 SDRAM is 533MHz (data rate 1066Mbps). The DDR3 memory
system is directly connected to the memory interface of the BANK 502 of the
ZYNQ Processing System (PS). The specific configuration of DDR3 SDRAM is
shown in Table 6-2.
Core Board Bit Number
AC7010
AC7020
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.
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ZYNQ Pin Name
PS_MIO6_500
PS_MIO1_500
PS_MIO2_500
PS_MIO3_500
PS_MIO4_500
PS_MIO5_500
model H5TQ2G63FFR-RDC
Chip Model
U8,U9 H5TQ2G63FFR-RDC
U8,U9 H5TQ4G63AFR-PBI
Table 6-2: DDR3 SDRAM Configuration
Amazon Store: https://www.amazon.com/alinx
ZYNQ Pin Number
A5
A7
B8
D6
B7
A6
(compatible
Capacity Factory
128M x 16bit SKhynix
256M x 16bit SKhynix
with