Pcie Interface - Quectel LTE-A Series Hardware Design

In addition, RI behavior can be configured flexibly. The default behavior of the RI is shown as below.
Table 24: RI Behaviors
State
Idle
URC
The RI behavior can be changed by executing AT+QCFG="urc/ri/ring" command. Please refer to
document [3] for more details.

3.17. PCIe Interface*

EG18 provides one integrated PCIe (Peripheral Component Interconnect Express) interface which
complies with the PCI Express Specification, Revision 2.1 and supports 5Gbps per lane. The PCIe
interface of EG18 is only used for data transmission.

PCI Express Specification Revision 2.1 compliance

Data rate at 5Gbps per lane

Can be used to connect to an external Ethernet IC (MAC and PHY) or WLAN IC
The following table shows the pin definition of PCIe interface.
Table 25: Pin Definition of the PCIe Interface
Pin Name
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_TX_M
PCIE_TX_P
PCIE_RX_M
PCIE_RX_P
EG18_Hardware_Design
Response
RI keeps at high level
RI outputs 120ms low pulse when a new URC returns
Pin No. I/O
179 AI/AO
180 AI/AO
182 AO
183 AO
185 AI
186 AI
Description
Input/Output PCIe
reference clock (+)
Input/Output PCIe
reference clock (-)
PCIe transmit (-)
PCIe transmit (+)
PCIe receive (-)
PCIe receive (+)
LTE-A Module Series
EG18 Hardware Design
Comment
If unused, keep it open.
If unused, keep it open.
If unused, keep it open.
If unused, keep it open.
If unused, keep it open.
If unused, keep it open.
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