Wlan_En; Pcie Interface - Quectel FG50V Hardware Design

3.5.1. WLAN_EN

WLAN_EN is used to control the WLAN function of FG50V module. WLAN function will be enabled when
WLAN_EN is at high level.
Table 5: Pin Definition of WLAN_EN
Pin Name Pin No.
WLAN_EN 84

3.5.2. PCIe Interface

The following table shows the pin definition of the PCIe interface of FG50V.
Table 6: Pin Definition of PCIe Interface
Pin Name
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_TX_P
PCIE_TX_M
PCIE_RX_P
PCIE_RX_M
PCIE_CLKREQ_N
PCIE_RST_N
PCIE_WAKE_N
FG50V_Hardware_Design
I/O Description
DI WLAN enable
Pin No. I/O Description
54 AI PCIe reference clock (+)
9 AI PCIe reference clock (-)
52 AO PCIe transmit (+)
7 AO PCIe transmit (-)
56 AI PCIe receive (+)
11 AI PCIe receive (-)
12 DO PCIe clock request
14 DI PCIe reset
13 DO PCIe wakes up
Wi-Fi&BT Module Series
FG50V Hardware Design
Comment
1.8 V power domain.
Active high.
It is suggested to pull down this pin
with a 100 kΩ resistor.
Comment
Require differential
impedance of 85 Ω.
1.8 V power domain.
Active low.
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