Quectel LTE-A Series Hardware Design page 28

PCM & I2C Interfaces
Pin Name Pin No.
I2C_SDA 42
I2C_SCL 43
PCM_SYNC 65
PCM_IN 66
PCM_CLK 67
PCM_OUT 68
I2S_MCLK 152
Antenna Interfaces
Pin Name Pin No.
ANT_MAIN 107
ANT_DIV 127
EG18_Hardware_Design
I/O Description
OD
I2C serial interface
used for external
OD
codec
PCM data frame
IO synchronization
signal
DI PCM data input
IO PCM clock
DO PCM data output
DO Clock output
I/O Description
Support all band main
IO
antenna interface
Support all band RXD
AI
antenna interface
EG18 Hardware Design
V min=1.2V
IH
V max=2.0V
IH
DC Characteristics
V max=0.45V
OL
V min=1.35V
OH
V min=-0.3V
IL
V max=0.6V
IL
V min=1.2V
IH
V max=2.0V
IH
V min=-0.3V
IL
V max=0.6V
IL
V min=1.2V
IH
V max=2.0V
IH
V max=0.45V
OL
V min=1.35V
OH
V min=-0.3V
IL
V max=0.6V
IL
V min=1.2V
IH
V max=2.0V
IH
V max=0.45V
OL
V min=1.35V
OH
DC Characteristics
LTE-A Module Series
open.
BT UART interface
pin by default.
Can be multiplexed
into SPI_CS.
Comment
1.8V power domain.
An external pull-up
resistor is required.
If unused, keep it open.
1.8V power domain.
In master mode, it is an
output signal. In slave
mode, it is an input
signal.
If unused, keep it open.
1.8V power domain.
If unused, keep it open.
1.8V power domain.
In master mode, it is an
output signal.
In slave mode, it is an
input signal.
If unused, keep it open.
1.8V power domain.
If unused, keep it open.
Provide a digital clock
output for an external
audio codec.
If unused, keep it open.
Comment
50Ω impedance
50Ω impedance
If unused, keep
27 / 104