Quectel LTE-A Series Hardware Design page 27
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Also See for LTE-A Series:
- Hardware design (88 pages) ,
- Manual (51 pages) ,
- Hardware design (83 pages)
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Debug UART Interface
Pin Name
Pin No.
DBG_RXD
136
DBG_TXD
137
BT UART Interface (Can be multiplexed into SPI interface*)
Pin Name
Pin No.
BT_EN
3
BT_TXD
163
BT_CTS
164
BT_RXD
165
BT_RTS
166
EG18_Hardware_Design
I/O
Description
DI
Receive data
DO
Transmit data
I/O
Description
BT function enable
DO
control
DO
Transmit data
DO
Clear to send
DI
Receive data
DI
Request to send
LTE-A Module Series
EG18 Hardware Design
DC Characteristics
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
DC Characteristics
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
min=-0.3V
IL
V
max=0.6V
IL
will wake up the
module.
If unused, keep it
open.
Comment
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
Comment
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
BT UART interface
pin by default.
Can be multiplexed
into SPI_MOSI.
1.8V power domain.
If unused, keep it
open.
BT UART interface
pin by default.
Can be multiplexed
into SPI_CLK.
1.8V power domain.
If unused, keep it
open.
BT UART interface
pin by default.
Can be multiplexed
into SPI_MISO.
1.8V power domain.
If unused, keep it
26 / 104
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