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Quectel FG50V Hardware Design

Wi-fi&bt module series
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FG50V
Hardware Design
Wi-Fi&BT Module Series
Version: 1.0
Date: 2020-12-08
Status: Released
www.quectel.com

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Summary of Contents for Quectel FG50V

  • Page 1 FG50V Hardware Design Wi-Fi&BT Module Series Version: 1.0 Date: 2020-12-08 Status: Released www.quectel.com...
  • Page 2 Unless otherwise provided by valid agreement, Quectel makes no warranties of any kind, implied or express, with respect to the use of features and functions under development. To the maximum extent permitted by law, Quectel excludes all liability for any loss or damage suffered in connection with the use of the functions and features under development, regardless of whether such loss or damage may have been foreseeable.
  • Page 3 Wi-Fi&BT Module Series FG50V Hardware Design The information contained here is proprietary technical information of Quectel. Transmitting, reproducing, disseminating and editing this document as well as using the content without permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design.

  • Page 4: About The Document

    Wi-Fi&BT Module Series FG50V Hardware Design About the Document Revision History Version Date Author Description Jared WANG/ 2019-11-25 Creation of the document Felix FU Hidy CHAI/ 2020-12-08 First official release Lucas HUANG FG50V_Hardware_Design 3 / 54...

  • Page 5: Table Of Contents

    Wi-Fi&BT Module Series FG50V Hardware Design Contents About the Document ............................3 Contents ................................ 4 Table Index ..............................6 Figure Index ..............................7 Introduction ............................8 1.1. Safety Information ..........................10 Product Concept ............................ 12 2.1. General Description ..........................12 2.2.
  • Page 6 Wi-Fi&BT Module Series FG50V Hardware Design 4.2. Electrical Characteristics ........................38 4.3. I/O Interface Characteristics ........................39 4.4. Operating and Storage Temperatures ....................40 4.5. Current Consumption ..........................40 4.5.1. Current Consumption in Low Power Modes ................40 4.5.2. Current Consumption in Normal Operation ................41 4.6.
  • Page 7 Wi-Fi&BT Module Series FG50V Hardware Design Table Index Table 1: Key Features ..............................12 Table 2: I/O Parameters Definition ..........................17 Table 3: Pin Description ............................. 17 Table 4: Definition of Power Supply and GND Pins ....................22 Table 5: Pin Definition of WLAN_EN .......................... 24 Table 6: Pin Definition of PCIe Interface ........................
  • Page 8 Figure 16: Mechanicals of UF.L-LP Connectors (Unit: mm) ..................36 Figure 17: Space Factor of Mated Connector (Unit: mm) ..................37 Figure 18: FG50V Top and Side Dimensions (Top and Side View) ................47 Figure 19: FG50V Bottom Dimension (Bottom View) ....................48 Figure 20: Recommended Footprint (Top View) .......................

  • Page 9: Introduction

    Wi-Fi&BT Module Series FG50V Hardware Design Introduction This document defines the FG50V module and describes its air interfaces and hardware interfaces which are connected with your application. This document can help you quickly understand module interface specifications, electrical and mechanical details, as well as other related information of the module.
  • Page 10 Wi-Fi&BT Module Series FG50V Hardware Design A certified modular has the option to use a permanently affixed label, or an electronic label. For a permanently affixed label, the module must be labeled with an FCC ID - Section 2.926 (see 2.2 Certification (labeling requirements) above).

  • Page 11: Safety Information

    The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating FG50V module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product.
  • Page 12 Wi-Fi&BT Module Series FG50V Hardware Design In locations with explosive or potentially explosive atmospheres, obey all posted signs and turn off wireless devices such as mobile phone or other cellular terminals. Areas with explosive or potentially explosive atmospheres include fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities, and areas where the air contains chemicals or particles such as grain, dust or metal powders.

  • Page 13: Product Concept

    FG50V Hardware Design Product Concept 2.1. General Description FG50V is a Wi-Fi and Bluetooth (BT) module with low power consumption. It is a single-die WLAN (Wireless Local Area Network) and BT combo solution supporting IEEE 802.11a/b/g/n/ac/ax 2.4/5 GHz WLAN standards and BT 5.1* standard, which enables seamless integration of WLAN and BT low energy technologies.
  • Page 14 Wi-Fi&BT Module Series FG50V Hardware Design 2.4 GHz 802.11b @ 11 Mbps: 20 dBm 802.11g @ 54 Mbps: 17 dBm 802.11n, HT20 @ MCS7: 16 dBm 802.11n, HT40 @ MCS7: 16 dBm 802.11ax, HE20 @ MCS11: 13 dBm 802.11ax, HE40 @ MCS11: 13 dBm...

  • Page 15: Functional Diagram

    Figure 1: Functional Diagram of FG50V Module 2.4. Evaluation Board In order to help you to develop applications with FG50V module conveniently, Quectel supplies the evaluation board (EVB), USB to RS-232 converter cable, USB data cable, power adapter, antenna and other peripherals to control or test the module.

  • Page 16: Application Interfaces

    Application Interfaces 3.1. General Description FG50V module is equipped with 108 LGA pins that can be connected to the cellular application platform. The subsequent chapters will provide a detailed introduction to the following interfaces and pins of the module: ...

  • Page 17: Pin Assignment

    Wi-Fi&BT Module Series FG50V Hardware Design 3.2. Pin Assignment Figure 2: Pin Assignment (Top View) FG50V_Hardware_Design 16 / 54...

  • Page 18: Pin Description

    Wi-Fi&BT Module Series FG50V Hardware Design NOTE Please keep all RESERVED pins open. 3.3. Pin Description The following tables show the pin description of FG50V module. Table 2: I/O Parameters Definition Type Description Analog Input Analog Input Digital Input Digital Output...
  • Page 19 Wi-Fi&BT Module Series FG50V Hardware Design 1.95 V power Vmin = 1.85 V It must be provided supply for the VDD_CORE_VH Vnorm = 1.95 V with sufficient current module’s main Vmax = 2.05 V of up to 0.4 A. part 1.8 V power...
  • Page 20 Wi-Fi&BT Module Series FG50V Hardware Design 1.8 V power domain. min = -0.3 V Active high. max = 0.63 V BT_EN BT enable It is suggested to pull min = 1.17 V down this pin with a max = 2.1 V 100 kΩ...
  • Page 21 Wi-Fi&BT Module Series FG50V Hardware Design 2.4G WWAN & WLAN/BT max = 0.45 V COEX_TXD coexistence min = 1.35 V transmit 2.4G WWAN & min = -0.3 V WLAN/BT max = 0.63 V COEX_RXD coexistence min = 1.17 V receive max = 2.1 V...

  • Page 22: Power Supply

    4, 5, 8, 10, 17, 18, 40, 49, 50, 53, 55, 58, 62, 64, 68, 71–73, 79 Keep these pins open. NOTE “*” means under development. 3.4. Power Supply The following table shows the power supply pins and ground pins of FG50V module. FG50V_Hardware_Design 21 / 54...
  • Page 23 Among them, VDD_CORE_VL, VDD_CORE_VM, VDD_CORE_VH, and VDD_IO can be powered by either Quectel RG50xQ series or discrete power supply chips while VDD_RF can be powered by a discrete power supply chip. The following figures show the two power designs. For more details, see document [2].

  • Page 24: Wlan Interface

    Wi-Fi&BT Module Series FG50V Hardware Design Figure 4: Power Reference Design with Discrete Power Supply Chips 3.5. WLAN Interface The following figure shows the WLAN interface connection between FG50V and the host. Figure 4: WLAN Interface Connection FG50V_Hardware_Design 23 / 54...

  • Page 25: Wlan_En

    Wi-Fi&BT Module Series FG50V Hardware Design 3.5.1. WLAN_EN WLAN_EN is used to control the WLAN function of FG50V module. WLAN function will be enabled when WLAN_EN is at high level. Table 5: Pin Definition of WLAN_EN Pin Name Pin No.

  • Page 26: Bt Interface

    Figure 5: PCIe Interface Connection To ensure the signal integrity of PCIe interface, C1 and C2 should be placed close to the FG50V module, and C3 and C4 should be placed close to the host The extra stubs of traces must be avoided.

  • Page 27: Bt_En

    NOTE The GPIO_1 connected to BT_WAKEUP_HOST must be interruptible. 3.6.1. BT_EN BT_EN is used to control the BT function of FG50V module. BT function will be enabled when BT_EN is at high level. Table 7: Pin Definition of BT_EN Pin Name Pin No.

  • Page 28: Pcm Interface

    1.8 V power domain. PCM_CLK PCM clock 1.8 V power domain. 1.8 V power domain. PCM_DOUT PCM data output Externally pull this pin up to VDD_IO. The following figure shows the PCM interface connection between FG50V and the host. FG50V_Hardware_Design 27 / 54...

  • Page 29: Uart Interface

    “*” means under development. 3.6.4. UART Interface FG50V supports an HCI UART as defined in Bluetooth Core Specification Version 4.0. In addition, the UART interface also supports software (in-band) sleep control of Bluetooth with Quectel RG50xQ series. You can also choose other 5G modules upon validation tests.

  • Page 30: Conexistence Interface

    Wi-Fi&BT Module Series FG50V Hardware Design 3.7. Conexistence Interface FG50V supports 2.4G WWAN & WLAN/BT coexistence (with coexistence UART) and 5G WWAN & WLAN coexistence. The following table shows the pin definition of coexistence interface. Table 9: Pin Definition of Coexistence Interface Pin Name Pin No.

  • Page 31: Wlan_Slp_Clk Interface

    The 32.768 kHz clock is used in low power modes, such as IEEE power saving mode and sleep mode. It serves as a timer to determine when to wake up the FG50V module to receive signals in various power saving schemes, and to maintain basic logic operations when the module is in sleep mode.

  • Page 32: Wlan Debug Interface

    Wi-Fi&BT Module Series FG50V Hardware Design NOTE “*” means under development. 3.9.2. WLAN Debug Interface The following table shows the pin definition of WLAN debug interface. Connect this interface to the test points in your application. Table 12: Pin Definition of WLAN Debug Interface Pin Name Pin No.

  • Page 33: Operating Frequency

    5.150–5.850 2.402–2.480 3.10.2. Reference Design of RF Antenna Interfaces FG50V provides three RF antenna interfaces for antenna connection. The following reference circuit design shows an example with ANT_WIFI0. For the other RF antenna interfaces, the reference design is the same.

  • Page 34: Reference Design Of Rf Layout

    Wi-Fi&BT Module Series FG50V Hardware Design Figure 10: Reference Circuit for RF Antenna Interfaces 3.10.3. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, the height from the reference ground to the signal layer (H), and the spacing between RF traces and grounds (S).
  • Page 35 Wi-Fi&BT Module Series FG50V Hardware Design Figure 12: Coplanar Waveguide Design on a 2-layer PCB Figure 13: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 14: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, the following principles should be complied with in RF layout design: ...

  • Page 36: Antenna Requirements

    Wi-Fi&BT Module Series FG50V Hardware Design the ground vias and RF traces should be no less than two times the width of RF signal traces (2 × W).  Keep RF traces away from interference sources, and avoid intersection and paralleling between traces on adjacent layers.
  • Page 37 Wi-Fi&BT Module Series FG50V Hardware Design Figure 15: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. Figure 16: Mechanicals of UF.L-LP Connectors (Unit: mm) The following figure describes the space factor of mated connector...
  • Page 38 Wi-Fi&BT Module Series FG50V Hardware Design Figure 17: Space Factor of Mated Connector (Unit: mm) For more details, visit http://www.hirose.com. FG50V_Hardware_Design 37 / 54...

  • Page 39: Reliability, Radio And Electrical Characteristics

    FG50V Hardware Design Reliability, Radio and Electrical Characteristics 4.1. General Description This chapter mainly introduces electrical and radio characteristics of FG50V module. The details are listed in the subsequent chapters. 4.2. Electrical Characteristics The following table shows the absolute maximum ratings.

  • Page 40: I/O Interface Characteristics

    Wi-Fi&BT Module Series FG50V Hardware Design The following table shows the recommended operating conditions of the module. Table 18: Recommended Operating Conditions Parameter Min. Typ. Max. Unit VDD_CORE_VL 0.95 VDD_CORE_VM 1.28 1.35 1.42 VDD_CORE_VH 1.85 1.95 2.05 VDD_IO VDD_RF 3.85 4.25...

  • Page 41: Operating And Storage Temperatures

    Wi-Fi&BT Module Series FG50V Hardware Design 4.4. Operating and Storage Temperatures Table 20: Operating and storage Temperatures Parameter Min. Typ. Max. Unit Operating Temperature Range ºC Storage Temperature Range ºC NOTE Within operating temperature range, the module is IEEE compliant.

  • Page 42: Current Consumption In Normal Operation

    Wi-Fi&BT Module Series FG50V Hardware Design 4.5.2. Current Consumption in Normal Operation Table 22: Current Consumption of the Module (Normal Operation, Unit: mA) VDD_CORE_V VDD_CORE_V VDD_CORE_V VDD_IO VDD_RF Description Conditions L (0.95 V) M (1.35 V) H (1.95 V) (1.8 V) (3.85 V)

  • Page 43: Rf Performances

    TX (5 GHz) 584.4 214.1 134.9 392.4 HE80 MCS11 4.6. RF Performances The following tables summarize the transmitting and receiving performances of FG50V. 4.6.1. Conducted RF Output Power Table 23: Conducted RF Output Power at 2.4 GHz Frequency Min. Typ. Unit 802.11b @ 1 Mbps...
  • Page 44 Wi-Fi&BT Module Series FG50V Hardware Design 802.11b @ 11 Mbps 17.5 802.11g @ 6 Mbps 18.5 802.11g @ 54 Mbps 14.5 802.11n, HT20 @ MCS0 18.5 802.11n, HT20 @ MCS7 13.5 802.11n, HT40 @ MCS0 15.5 802.11n, HT40 @ MCS7 13.5...

  • Page 45: Conducted Rf Receiving Sensitivity

    Wi-Fi&BT Module Series FG50V Hardware Design 802.11ac, VHT80 @ MCS9 11.5 802.11ax, HE20 @ MCS0 17.5 802.11ax, HE20 @ MCS11 10.5 802.11ax, HE40 @ MCS0 17.5 802.11ax, HE40 @ MCS11 10.5 802.11ax, HE80 @ MCS0 17.5 802.11ax, HE80 @ MCS11 10.5...

  • Page 46: Electrostatic Discharge

    Wi-Fi&BT Module Series FG50V Hardware Design Table 26: Conducted RF Receiving Sensitivity at 5 GHz Frequency Receiving Sensitivity (Typ.) 802.11a @ 6 Mbps -94 dBm 802.11a @ 54 Mbps -75 dBm 802.11n, HT20 @ MCS0 -93 dBm 802.11n, HT20 @ MCS7 -75 dBm 802.11n, HT40 @ MCS0...
  • Page 47 Wi-Fi&BT Module Series FG50V Hardware Design The following table shows the module electrostatic discharge characteristics. Table 27: Electrostatic Discharge Characteristics Tested Points Contact Discharge Air Discharge Unit VDD_RF, GND ±6 ±10 Antenna Interfaces ±6 ±10 Other Interfaces ±0.5 ±1 FG50V_Hardware_Design...

  • Page 48: Mechanical Dimensions

    Wi-Fi&BT Module Series FG50V Hardware Design Mechanical Dimensions This chapter describes the mechanical dimensions of FG50V module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ±0.05 mm unless otherwise specified. 5.1. Mechanical Dimensions of the Module...
  • Page 49 Wi-Fi&BT Module Series FG50V Hardware Design Pin1 Figure 19: FG50V Bottom Dimension (Bottom View) NOTE The package warpage level of the module conforms to JEITA ED-7306 standard. FG50V_Hardware_Design 48 / 54...

  • Page 50: Recommended Footprint

    Wi-Fi&BT Module Series FG50V Hardware Design 5.2. Recommended Footprint Pin1 Figure 20: Recommended Footprint (Top View) NOTES 1. For easy maintenance of this module, keep at least 3 mm between the module and other components on the motherboard. 2. Keep all RESERVED pins open.

  • Page 51: Top And Bottom Views Of The Module

    Figure 21: Top View of the Module Figure 22: Bottom View of the Module NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. FG50V_Hardware_Design 50 / 54...

  • Page 52: Storage, Manufacturing And Packaging

    Wi-Fi&BT Module Series FG50V Hardware Design Storage, Manufacturing and Packaging 6.1. Storage The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity should be 35–60 %.

  • Page 53: Manufacturing And Soldering

    Wi-Fi&BT Module Series FG50V Hardware Design This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. 2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules to the air for a long time. If the temperature and moisture do not conform to IPC/JEDEC J-STD-033 or the relative moisture is over 60%, it is recommended to start the solder reflow process within 24 hours after the package is removed.

  • Page 54: Packaging

    Max reflow cycle 6.3. Packaging FG50V is packaged in tape and reel carriers. Each reel is 330 mm in diameter and contains 200 modules. The dimensions of tape and reel will be added in the updated version of this document.

  • Page 55: Appendix References

    Wi-Fi&BT Module Series FG50V Hardware Design Appendix References Table 29: Related Documents Document Name Description Quectel_5G_EVB_User_Guide EVB user guide for Quectel 5G modules Quectel_FG50V_Reference_Design FG50V reference design Quectel_RF_Layout_Application_Note RF layout application note Quectel_RG500Q_Series_Wi-Fi_Application_Note FG50V Wi-Fi_application note Quectel_Module_Secondary_SMT_Application_Note Module secondary SMT application note...
  • Page 56 Wi-Fi&BT Module Series FG50V Hardware Design High Efficiency High Throughput IEEE Institute of Electrical and Electronics Engineers Input Leakage Current Input/Output Low-Noise Amplifier Long Term Evolution Mbps Megabits per second Modulation and Coding Scheme Minimum Order Quantity Power Amplifier Printed Circuit Board...
  • Page 57 Wi-Fi&BT Module Series FG50V Hardware Design Minimum Input High Level Voltage Value Maximum Input Low Level Voltage Value Minimum Input Low Level Voltage Value Maximum Output Low Level Voltage Value Minimum Output High Level Voltage Value VSWR Voltage Standing Wave Ratio...

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