Spi Interface - Quectel LTE-A Series Hardware Design

Another example with transistor translation circuit is shown as below. The circuit designs for the parts
shown with dotted lines refer to the design of TXD and RXD, and please pay attention to the direction of
connection.
MCU/ARM
Figure 25: Level Translation Reference Circuit with MOSFETs
NOTE
Transistor circuit solution is not suitable for applications with high baud rates exceeding 460kbps.

3.11. SPI Interface*

EG18 provides one SPI interface multiplexed from BT UART interface. The interface only supports master
mode with a maximum clock frequency up to 50MHz. The following table shows the pin definition of SPI
interface.
Table 16: Pin Definition of SPI Interface
Pin Name Pin No.
BT_TXD 163
BT_CTS 164
EG18_Hardware_Design
VDD_EXT
TXD
RXD
10K
VCC_MCU
RTS
CTS
GPIO
EINT
GPIO
GND
I/O Description
DO Can be multiplexed into SPI_MOSI.
DO Can be multiplexed into SPI_CLK.
4.7K
VDD_EXT
1nF
10K
1nF
VDD_EXT
4.7K
LTE-A Module Series
EG18 Hardware Design
Module
RXD
TXD
RTS
CTS
DTR
RI
DCD
GND
Comment
1.8V power domain
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