Quectel LTE-A Series Hardware Design page 57

PCM_CLK
PCM_SYNC
PCM_OUT
PCM_IN
The following table shows the pin definition of PCM interface and I2C interface, both of which can be
applied on audio codec design.
Table 18: Pin Definition of PCM interface and I2C Interface
Pin Name Pin No.
PCM_IN 66
PCM_OUT 68
PCM_SYNC 65
PCM_CLK 67
I2C_SDA 42
I2C_SCL 43
I2S_MCLK 152
EG18_Hardware_Design
125μs
1 2
MSB
MSB
Figure 28: Auxiliary Mode Timing
I/O Description
DI PCM data input
DO PCM data output
PCM data frame
IO
synchronization signal
IO PCM data clock
OD I2C serial data
OD I2C serial clock
DO Clock output
LTE-A Module Series
EG18 Hardware Design
31 32
LSB
LSB
Comment
1.8V power domain.
If unused, keep it open.
1.8V power domain.
If unused, keep it open.
1.8V power domain.
In master mode, it is an output signal.
In slave mode, it is an input signal.
If unused, keep it open.
1.8V power domain.
In master mode, it is an output signal.
In slave mode, it is an input signal.
If unused, keep it open.
An external pull-up resistor is required.
If unused, keep it open.
An external pull-up resistor is required.
If unused, keep it open.
Provide a digital clock output for an
external audio codec.
If unused, keep it open.
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