Quectel LTE-A Series Hardware Design page 55

BT_RXD 165
BT_RTS 166
The following figure shows the timing of SPI Interface.
The related parameters of SPI timing are listed in the following table.
Table 17: Parameters of SPI Interface Timing
Parameter Description
T SPI clock period
t(ch) SPI clock high level time
t(cl) SPI clock low level time
t(mov) SPI master data output valid time
t(mis) SPI master data input setup time
t(mih) SPI master data input hold time
NOTE
"*" means under development.
EG18_Hardware_Design
DI Can be multiplexed into SPI_MISO.
DI Can be multiplexed into SPI_CS.
Figure 26: Timing of SPI Interface
EG18 Hardware Design
Min. Typ.
20.0 -
9.0 -
9.0 -
-5.0 -
5.0 -
1.0 -
LTE-A Module Series
Max. Unit
- ns
- ns
- ns
5.0 ns
- ns
- ns
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