Quectel LTE-A Series Hardware Design page 30
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Also See for LTE-A Series:
- Hardware design (88 pages) ,
- Manual (51 pages) ,
- Hardware design (86 pages)
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PCIe Interface*
Pin Name
Pin No.
PCIE_REFCLK_P 179
PCIE_REFCLK_
180
M
PCIE_TX_M
182
PCIE_TX_P
183
PCIE_RX_M
185
PCIE_RX_P
186
PCIE_CLK_
188
REQ_N
PCIE_RST_N
189
PCIE_WAKE_N
190
GPIO Pins
Pin Name
Pin No.
GPIO_1
138
GPIO_2
139
EG18_Hardware_Design
I/O
Description
AI/
Input/Output PCIe
AO
reference clock (+)
AI/
Input/Output PCIe
AO
reference clock (-)
AO
PCIe transmission (-)
AO
PCIe transmission (+)
AI
PCIe receiving (-)
AI
PCIe receiving (+)
IO
PCIe clock request
IO
PCIe reset
IO
PCIe wake up
I/O
Description
IO
General purpose
input/output port
IO
LTE-A Module Series
EG18 Hardware Design
DC Characteristics
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=2.0V
IH
DC Characteristics
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
Comment
Comply with PCIe
2.1 standard
specifications.
Require differential
impedance of 95Ω.
In master mode, it is
an input signal.
In slave mode, it is
an output signal.
If unused, keep it
open.
In master mode, it is
an output signal.
In slave mode, it is
an input signal.
If unused, keep it
open.
In master mode, it is
an input signal.
In slave mode, it is
an output signal.
If unused, keep it
open.
Comment
If unused, keep
them open.
29 / 104
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