Debug Uart Interface; Bt Uart Interface; Uart Application - Quectel LTE-A Series Hardware Design
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3.10.2. Debug UART Interface
The following table shows the pin definition of debug UART interface.
Table 13: Pin Definition of Debug UART Interface
Pin Name
Pin No.
DBG_RXD
136
DBG_TXD
137
3.10.3. BT UART Interface
The following table shows the pin definition of BT UART interface.
Table 14: Pin Definition of the BT UART Interface
Pin Name
Pin No.
BT_EN
3
BT_TXD
163
BT_CTS
164
BT_RXD
165
BT_RTS
166
3.10.4. UART Application
EG18 provides 1.8V UART interfaces. A level translator should be used if the application is equipped with
a 3.3V UART interface.
The logic levels are described in the following table.
Table 15: Logic Levels of Digital I/O
Parameter
V
IL
EG18_Hardware_Design
I/O
Description
DI
Receive data
DO
Transmit data
I/O
Description
DO
BT function enable control
DO
Transmit data
DO
Clear to send
DI
Receive data
DI
Request to send
Min.
-0.3
LTE-A Module Series
EG18 Hardware Design
Comment
1.8V power domain
1.8V power domain
Comment
1.8V power domain
If unused, keep it open.
Max.
0.6
Unit
V
51 / 104
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