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Quectel QuecOpen AG521R-NA Hardware Design

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AG521R-NA
Hardware Design
Automotive Module Series
Version: 1.0.0
Date: 2021-01-26
Status: Preliminary
QuecOpen
www.quectel.com

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Summary of Contents for Quectel QuecOpen AG521R-NA

  • Page 1 AG521R-NA QuecOpen Hardware Design Automotive Module Series Version: 1.0.0 Date: 2021-01-26 Status: Preliminary www.quectel.com...
  • Page 2 Disclaimer While Quectel has made efforts to ensure that the functions and features under development are free from errors, it is possible that these functions and features could contain errors, inaccuracies and omissions. Unless otherwise provided by valid agreement, Quectel makes no warranties of any kind, implied or express, with respect to the use of features and functions under development.
  • Page 3 Automotive Module Series AG521R-NA QuecOpen Hardware Design The information contained here is proprietary technical information of Quectel Wireless Solutions Co., Ltd. Transmitting, reproducing, disseminating and editing this document as well as using the content without permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design.

  • Page 4: About The Document

    Automotive Module Series AG521R-NA QuecOpen Hardware Design About the Document Revision History Version Date Author Description Leon HUANG/ 2020-04-04 Alex ZHANG/ Evan Creation of the document SHEN/ Charlie Bao/ 2021-01-26 Jacky CHEN/ Evan Preliminary SHEN AG521R-NA_QuecOpen_Hardware_Design 3 / 104...

  • Page 5: Table Of Contents

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Contents About the Document ..............................3 Contents ..................................4 Table Index .................................. 6 Figure Index ................................8 Introduction ..............................10 1.1. Safety Information ..........................12 Product Concept ............................... 14 2.1. General Description ..........................14 2.2.
  • Page 6 Automotive Module Series AG521R-NA QuecOpen Hardware Design 3.13. SDIO Interface ............................55 3.14. SPI Interfaces ............................58 3.15. RGMII Interface ............................. 59 3.16. WLAN and BT Interfaces* ........................62 3.17. ADC Interfaces ............................65 3.18. USB_BOOT Interface ..........................66 3.19. GPIO Interfaces ............................66 Antenna Interfaces............................
  • Page 7 Automotive Module Series AG521R-NA QuecOpen Hardware Design Table Index ® Table 1: Frequency Bands of AG521R-NA QuecOpen Module ................14 Table 2: Key Features ..............................15 Table 3: I/O Parameters Definition ..........................21 Table 4: Pin Description ............................22 Table 5: Alternate Functions of Multiplexing Pins ....................33 Table 6: Overview of Operating Modes ........................
  • Page 8 Automotive Module Series AG521R-NA QuecOpen Hardware Design Table 42: GPRS Multi-slot Classes ........................... 92 Table 43: EDGE Modulation and Coding Schemes ....................92 AG521R-NA_QuecOpen_Hardware_Design 7 / 104...
  • Page 9 Automotive Module Series AG521R-NA QuecOpen Hardware Design Figure Index ® Figure 1: Functional Diagram for AG521R-NA QuecOpen ..................18 Figure 2: Pin Assignment (Top View) ........................20 Figure 3: Sleep Mode Current Consumption Diagram ....................38 Figure 4: Sleep Mode Application with USB Remote Wakeup ................. 38 Figure 5: Sleep Mode Application without USB Remote Wakeup ................
  • Page 10 Automotive Module Series AG521R-NA QuecOpen Hardware Design Figure 42: Top View of the Module ........................... 84 Figure 43: Bottom View of the Module ........................84 Figure 44: Recommended Reflow Soldering Thermal Profile .................. 86 Figure 45: Tape Specifications ..........................88 Figure 46: Reel Specifications ...........................

  • Page 11: Introduction

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Introduction ® QuecOpen is an application solution where the module acts as a main processor. With the development of communication technology and the ever-changing market demands, more and more customers have realized the ®...
  • Page 12 Automotive Module Series AG521R-NA QuecOpen Hardware Design Band LTE BAND 2 8.00 8.00 LTE BAND 4 8.00 8.00 LTE BAND 5 5.00 5.00 LTE BAND 7 8.00 8.00 LTE B12 5.00 5.00 LTE B13 5.00 5.00 LTE B14 5.00 5.00 LTE B25 8.00 5.00...

  • Page 13: Safety Information

    Automotive Module Series AG521R-NA QuecOpen Hardware Design equipment. To ensure compliance with all non-transmitter functions the host manufacturer is responsible for ensuring compliance with the module(s) installed and fully operational. For example, if a host was previously authorized as an unintentional radiator under the Supplier’s Declaration of Conformity procedure without a transmitter certified module and a module is added, the host manufacturer is responsible for ensuring that the after the module is installed and operational the host continues to be compliant with the Part 15B unintentional radiator requirements.
  • Page 14 Automotive Module Series AG521R-NA QuecOpen Hardware Design of the product. Otherwise, Quectel assumes no liability for customers’ failure to comply with these precautions. Full attention must be paid to driving at all times in order to reduce the risk of an accident.

  • Page 15: Product Concept

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Product Concept 2.1. General Description AG521R-NA QuecOpen module is a baseband processor platform based on ARM Cortex A7 kernel. The maximum dominant frequency is up to 1.497 GHz. AG521R-NA QuecOpen module is a series of automotive-grade LTE-FDD wireless communication modules with receive diversity.

  • Page 16: Key Features

    Automotive Module Series AG521R-NA QuecOpen Hardware Design LTE-FDD B29, B30 and B32 support Rx only. 2.2. Key Features The following table describes detailed features of the module. Table 2: Key Features Feature Details VBAT_BB/VBAT_RF: ⚫ Power Supply Supply voltage: 3.3–4.3 V ⚫...
  • Page 17 Automotive Module Series AG521R-NA QuecOpen Hardware Design ⚫ Used for AT command communication, data transmission, firmware upgrade, software debugging, and voice over USB* ⚫ Support USB serial drivers for: Windows 7/8/8.1/10, Linux 2.6~5.4, and Android 4.x/5.x/6.x/7.x/8.x/9.x UART1: ⚫ Baud rate reach up to 921600 bps, 115200 bps by default ⚫...

  • Page 18: Functional Diagram

    Automotive Module Series AG521R-NA QuecOpen Hardware Design and maintain functions such as voice, SMS, data transmission and emergency call, without any unrecoverable malfunction. Radio spectrum and radio network will not be influenced, while one or more specifications, such as P , may undergo a reduction in value, exceeding the specified tolerances of 3GPP.

  • Page 19: Evaluation Board

    Figure 1: Functional Diagram for AG521R-NA QuecOpen 2.4. Evaluation Board To help you develop applications conveniently with the module, Quectel supplies the evaluation board (EVB), USB data cables, a pair of earphones, antennas and other peripherals to control or test the module. For more details, see document [1].

  • Page 20: Application Interfaces

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Application Interfaces 3.1. General Description The module is designed with 400 LGA pins that can be connected to cellular application platforms. Module interfaces are described in detail in the following sub-chapters: ⚫ Power supply ⚫...

  • Page 21: Pin Assignment

    Automotive Module Series AG521R-NA QuecOpen Hardware Design 3.2. Pin Assignment RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SPI1_MOSI SPI1_CS RESERVED RESERVED RESERVED SPI1_CLK SPI1_MISO GPIO5 WLAN_PWR_EN1 RESERVED RESERVED VBAT_RF RESERVED VBAT_RF WLAN_PWR_EN2 DBG_RXD RESERVED VBAT_RF RESERVED VBAT_RF WLEN_EN DBG_TXD RESERVED RESERVED RESERVED WLAN_SLP_CLK GPIO4...

  • Page 22: Pin Description

    Automotive Module Series AG521R-NA QuecOpen Hardware Design NOTES Keep all RESERVED pins and unused pins unconnected. GND pins should be connected to ground in the design. 3.3. Pin Description The following tables show the pin definition of the module and the alternate functions of multiplexing pins. Table 3: I/O Parameters Definition Type Description...
  • Page 23 Automotive Module Series AG521R-NA QuecOpen Hardware Design Table 4: Pin Description Power Supply Pin Name Pin No. Description Comment Characteristics Power supply for the Vmax = 4.3 V It must be provided 241, 242, module’s baseband VBAT_BB Vmin = 3.3 V with sufficient current part Vnorm = 3.8 V...
  • Page 24 Automotive Module Series AG521R-NA QuecOpen Hardware Design max = 50 mA For 1.8 V (U)SIM: Either 1.8 V or 3.0 V Vmax = 1.9 V is supported by the (U)SIM1 card power Vmin = 1.7 V USIM1_VDD module automatically. supply If unused, keep it For 3.0 V (U)SIM: open.
  • Page 25 Automotive Module Series AG521R-NA QuecOpen Hardware Design max = 50 mA For 1.8 V (U)SIM: max = 0.36 V min = 1.26 V max = 0.4 V min = 1.44 V If unused, keep it USIM2_DATA (U)SIM2 card data open. For 3.0 V (U)SIM: max = 0.57 V min = 2.0 V...
  • Page 26 Automotive Module Series AG521R-NA QuecOpen Hardware Design USB 3.0 super-speed USB_SS_TX_P transmit (+) Compliant with USB USB 3.0 super-speed USB_SS_TX_M 3.0 standard transmit (-) specification. Require USB 3.0 super-speed differential impedance USB_SS_RX_P receive (+) of 90 Ω. USB 3.0 super-speed USB_SS_RX_M receive (-) GPIO Interfaces...
  • Page 27 Automotive Module Series AG521R-NA QuecOpen Hardware Design max = 0.45 V UART1_TXD UART1 transmit min = 1.35 V min = -0.3 V max = 0.63 V UART1_RXD UART1 receive min = 1.17 V max = 2.1 V BT UART Interface Pin Name Pin No.
  • Page 28 Automotive Module Series AG521R-NA QuecOpen Hardware Design I2S Interface (for Codec Configuration by Default) Pin Name Pin No. Description Comment Characteristics max = 0.45 V CDC_RST Codec reset min = 1.35 V Clock output for max = 0.45 V I2S_MCLK codec min = 1.35 V max = 0.45 V...
  • Page 29 Automotive Module Series AG521R-NA QuecOpen Hardware Design PCIe Interface Pin Name Pin No. Description Comment Characteristics PCIE_REFCLK_ PCIe reference clock PCIE_REFCLK_ PCIe reference clock Require differential impedance of 95 Ω. PCIE_TX_M PCIe transmit (-) If unused, keep them PCIE_TX_P PCIe transmit (+) open.
  • Page 30 Automotive Module Series AG521R-NA QuecOpen Hardware Design RGMII receive data RGMII_RX_3 bit 3 RGMII_CK_RX RGMII receive clock RGMII transmit data RGMII_TX_0 bit 0 RGMII transmit RGMII_CTL_TX 21 control RGMII transmit data RGMII_TX_1 bit 1 RGMII transmit data RGMII_TX_2 bit 2 RGMII_CK_TX RGMII transmit clock RGMII transmit data...
  • Page 31 Automotive Module Series AG521R-NA QuecOpen Hardware Design SDC1_CMD SDIO command SDC1_DATA_4 SDIO data bit 4 max = 0.45 V min = 1.35 V 1.8 V power domain SDC1_DATA_5 SDIO data bit 5 min = -0.3 V Can be configured to max = 0.63 V SDC1_DATA_6 SDIO data bit 6...
  • Page 32 Automotive Module Series AG521R-NA QuecOpen Hardware Design Pin Name Pin No. Description Comment Characteristics Force the module into USB_BOOT emergency download 1.8 V power domain. mode If unused, keep it BT function enable max = 0.45 V BT_EN open. control min = 1.35 V Navigation 1PPS time max = 0.45 V...
  • Page 33 Automotive Module Series AG521R-NA QuecOpen Hardware Design Pin Name Pin No. Description Comment Characteristics Main antenna ANT_MAIN interface 50 Ω impedance. Diversity antenna ANT_DIV interface RESERVED Pins Pin Name Pin No. Comment 1-6, 9, 35, 37, 41, 43, 64, 65, 82, 89, 94, 96, 97, 99, 103, 105, 106, 108, 113, 119, 122, 123, 132, 136, 139, 142, 152, 154, 157, 161, 163, 166, 175, 178, 179, 184, 188, 190, 193, 196, 197, 200, 204, RESERVED...
  • Page 34 Automotive Module Series AG521R-NA QuecOpen Hardware Design Table 5: Alternate Functions of Multiplexing Pins Default Wake up Pin Name Alternate Function 1 Alternate Function 2 Reset Power Domain Remark Function Interrupt RGMII_PWR_EN BS-PD, L 1.8 V RGMII_INT RGMII BS-PD, L 1.8 V RGMII_RST BS-PD, L...
  • Page 35 Automotive Module Series AG521R-NA QuecOpen Hardware Design UART1_CTS GPIO_23 BS-PD, L 1.8 V UART1_RXD GPIO_21 BS-PU, L 1.8 V UART1_RTS GPIO_22 BS-PD, L 1.8 V DBG_TXD BS-PD, L 1.8 V DBG_RXD BS-PD, L 1.8 V PCM_SYNC I2S_WS GPIO_12 BS-PD, L 1.8 V PCM_CLK I2S_SCK...
  • Page 36 Automotive Module Series AG521R-NA QuecOpen Hardware Design USIM2_CLK BSH-PD, L 1.8/2.85 V USIM2_DATA BSH-PD, L 1.8/2.85 V USIM2_DET BS-PD, L 1.8 V SPI1_MOSI GPIO_72 BS-PD, L 1.8 V SPI1_CS GPIO_74 BS-PD, L 1.8 V SPI1_CLK GPIO_75 BS-PD, L 1.8 V SPI1_MISO GPIO_73 BS-PD, L...
  • Page 37 Automotive Module Series AG521R-NA QuecOpen Hardware Design GPIO7 BS-PD, L 1.8 V GPIO8 1.8 V NOTES 1. “Alternate Function 1/2” takes effect only after software configuration. See Table 4 for more details about the symbol description. If the GPIOs without interrupt function are configured as interrupt GPIOs, power consumption of the module will be increased. (“Y” means “interrupt function supported”. “N” means “interrupt function not supported”.) 4.

  • Page 38: Operating Modes

    Automotive Module Series AG521R-NA QuecOpen Hardware Design 3.4. Operating Modes The table below briefly summarizes the various operating modes referred in the following chapters. Table 6: Overview of Operating Modes Mode Details Software is active. The module has registered on the network, and it is Idle ready to send and receive data.

  • Page 39: Usb Application With Usb Remote Wakeup Function

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Figure 3: Sleep Mode Current Consumption Diagram NOTE DRX cycle index values are broadcasted by the base station through the wireless network. 3.5.1.1. USB Application with USB Remote Wakeup Function If the host supports USB suspend/resume and remote wakeup function, the following three preconditions must be met to let the module enter sleep mode.

  • Page 40: Usb Application Without Usb Suspend Function

    Automotive Module Series AG521R-NA QuecOpen Hardware Design ⚫ Use sleep & wakeup API to enable the sleep mode. ⚫ Ensure the level of pins that configured as wake-up interrupt in Table 5 are under non-wakeup status. ⚫ The host’s USB bus, which is connected with the module’s USB interface, enters suspended state. The following figure shows the connection between the module and the host.

  • Page 41: Airplane Mode

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Figure 6: Sleep Mode Application without Suspend Function Switching on the power switch to supply power to USB_VBUS will wake up the module. NOTE Please pay attention to the level match shown in dotted line between the module and the host. 3.5.2.

  • Page 42: Decrease Voltage Drop

    Automotive Module Series AG521R-NA QuecOpen Hardware Design 3.6.2. Decrease Voltage Drop The power supply range of the module is from 3.3 to 4.3 V. Please make sure that the input voltage will never drop below 3.3 V. The following figure shows the voltage drop during burst transmission in 2G network. The voltage drop will be less in 3G and 4G networks.

  • Page 43: Reference Design For Power Supply

    Automotive Module Series AG521R-NA QuecOpen Hardware Design 3.6.3. Reference Design for Power Supply Power design for the module is very important, as the performance of the module largely depends on the power source. If the voltage drop between the input and output is not too high, it is recommended to use an LDO to supply power for the module.
  • Page 44 Automotive Module Series AG521R-NA QuecOpen Hardware Design max = 1.89 V 1.8 V power domain. PWRKEY Turn on/off the module min = 1.17 V Pulled-up internally. max = 0.63 V Active low. When the module is in power-off mode, it can be turned on by driving PWRKEY low for at least 500 ms. It is recommended to use an open drain/collector driver to control the PWRKEY.

  • Page 45: Turn On Module With Pon_1

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Note 1 ≥ 500 ms VBAT ≥ 1.17 V PWRKEY ≤ 0.63 V RESET UART I nactive Active I nactive Active VDD_ EXT Figure 12: Power-on Timing NOTES 1. Please make sure that VBAT is stable for at least 30 ms before pulling down PWRKEY pin. 2.

  • Page 46: Turn Off Module

    Automotive Module Series AG521R-NA QuecOpen Hardware Design PON_1 0.78– 1.89 V PVIN SS/TR Module Figure 13: Turn on the Module using PON_1 NOTE If PON_1 is not used, it is recommended to connect it to the ground. 3.7.3. Turn off Module Either of the following methods can be used to turn off the module: ⚫...

  • Page 47: Turn Off Module Using Api Interface

    Automotive Module Series AG521R-NA QuecOpen Hardware Design 3.7.3.2. Turn off Module Using API Interface It is also a safe way to use API interface to turn off the module, which is similar to turning off the module via PWRKEY Pin. See document [2] for details about API function.
  • Page 48 Automotive Module Series AG521R-NA QuecOpen Hardware Design RESET 370– 620 ms 4.7K Reset pulse Figure 15: Reference Circuit of RESET by Using Driving Circuit RESET Close to S2 Figure 16: Reference Circuit of RESET by Using Button The reset scenario is illustrated in the following figure. VBAT 620 ms ≥...

  • Page 49: U)Sim Interfaces

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Please assure that there is no large capacitance on PWRKEY and RESET pins. 3.9. (U)SIM Interfaces The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both 1.8 V and 3.0 V (U)SIM cards are supported.
  • Page 50 Automotive Module Series AG521R-NA QuecOpen Hardware Design VDD_EXT USIM_VDD 470K 100 nF (U)SIM Card Connector USIM_VDD USIM_RST Module USIM_CLK USIM_DET USIM_DATA 33 pF 33 pF33 pF Figure 18: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, keep USIM_DET disconnected. A reference circuit for (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following figure.

  • Page 51: Usb Interfaces

    Automotive Module Series AG521R-NA QuecOpen Hardware Design with surrounded ground. ⚫ In order to offer good ESD protection, it is recommended to add a TVS diode array with parasitic capacitance not exceeding 10 pF. The 22 Ω resistors should be added in series between the module and the (U)SIM card connector so as to suppress EMI spurious transmission and enhance ESD protection.
  • Page 52 Automotive Module Series AG521R-NA QuecOpen Hardware Design Test Points Minimize these stubs Module Connector NM_0R NM_0R USB_VBUS USB_VBUS USB_DM USB_DM USB_DP USB_DP Close to Module ESD Array Figure 20: Reference Circuit of USB 2.0 Application USB_VBUS USB_VBUS 100 nF USB_SS_TX_P USB_SS_RX_P 100 nF USB_SS_TX_M...

  • Page 53: Uart Interfaces

    Automotive Module Series AG521R-NA QuecOpen Hardware Design ⚫ Do not route signal traces under crystals, oscillators, magnetic devices, PCIe and RF signal traces. It is important to route the USB differential traces in inner-layer with ground shielding on not only upper and lower layers but also right and left sides.
  • Page 54 Automotive Module Series AG521R-NA QuecOpen Hardware Design Can be configured to GPIOs BT_UART_RXD BT UART receive BT_UART_RTS BT UART request to send BT_UART_CTS BT UART clear to send Table 15: Pin Definition of Debug UART Interface Pin Name Pin No. Description Comment DBG_TXD...

  • Page 55: I2S And I2C Interfaces

    Automotive Module Series AG521R-NA QuecOpen Hardware Design attention to the direction of connection. 4.7K VDD_1V8 VDD_1V8 1 nF MCU/ARM Module 1 nF VDD_1V8 VCC_MCU 4.7K Figure 23: Reference Circuit with Transistor Circuit NOTES 1. Transistor circuit solution is not suitable for applications with high baud rates exceeding 460 kbps. 2.

  • Page 56: Sdio Interface

    Automotive Module Series AG521R-NA QuecOpen Hardware Design I2S_DOUT I2S data out Table 18: Pin Definition of I2C Interface Pin Name Pin No. Description Comment I2C1_SCL I2C serial clock Require external pull-up to 1.8 V. I2C1_SDA I2C serial data The following figure shows a reference design of I2S and I2C interfaces with an external codec IC. CDC_RST RESET I2S_MCLK...
  • Page 57 Automotive Module Series AG521R-NA QuecOpen Hardware Design SDIO_VDD SDIO power supply Connect it to VDD_EXT. SDC1_DATA_0 SDIO data bit 0 SDC1_DATA_1 SDIO data bit 1 SDC1_DATA_2 SDIO data bit 2 1.8 V power domain for eMMC. SDC1_DATA_3 SDIO data bit 3 SDC1_CMD SDIO command SDC1_DATA_4...
  • Page 58 Automotive Module Series AG521R-NA QuecOpen Hardware Design VDD_1V8 VDD_1.8V R1 0R SDC1_DATA_0 DAT0 VCCQ R2 0R SDC1_DATA_1 DAT1 1 µF 100 nF R3 0R SDC1_DATA_2 DAT2 VDD_3V R4 0R SDC1_DATA_3 DAT3 R5 0R SDC1_DATA_4 DAT4 100 nF 2.2 µF R6 0R SDC1_DATA_5 DAT5 R7 0R...

  • Page 59: Spi Interfaces

    Automotive Module Series AG521R-NA QuecOpen Hardware Design 3.14. SPI Interfaces The module provides two SPI interfaces supporting only master mode. The maximum clock frequency of SPI is up to 50 MHz. Table 20: Pin Definition of SPI Interfaces Pin Name Pin No.

  • Page 60: Rgmii Interface

    Automotive Module Series AG521R-NA QuecOpen Hardware Design t(cl) SPI clock low-level time t(mov) SPI master data output valid time -5.0 t(mis) SPI master data input setup time t(mih) SPI master data input hold time NOTE The module provides a 1.8 V SPI interface. A level translator should be used between the module and the host if customers’...
  • Page 61 Automotive Module Series AG521R-NA QuecOpen Hardware Design RGMII_TX_0 RGMII transmit data bit 0 RGMII_CTL_TX RGMII transmit control RGMII_TX_1 RGMII transmit data bit 1 RGMII_TX_2 RGMII transmit data bit 2 RGMII_CK_TX RGMII transmit clock RGMII_TX_3 RGMII transmit data bit 3 Enable external LDO to supply RGMII_PWR_EN 1.8 V power domain power to RGMII_PWR_IN...
  • Page 62 Automotive Module Series AG521R-NA QuecOpen Hardware Design RGMII_VDDO RGMII_MD_IO MDIO RGMII_MD_CLK INTN RGMII_INT RGMII_RST RESETN R1 0R RGMII_RX_0 RXD0 R2 0R RGMII_RX_1 RXD1 R3 0R RGMII_RX_2 RXD2 R4 0R RGMII_RX_3 RXD3 R5 0R RGMII_CTL_RX R6 0R RGMII_CK_RX RCLK R7 0R RGMII_TX_0 TXD0 R8 0R...

  • Page 63: Wlan And Bt Interfaces

    Automotive Module Series AG521R-NA QuecOpen Hardware Design The value of R1–R16 varies with the selection of PHY. 3.16. WLAN and BT Interfaces* The module provides a PCIe interface for WLAN function and UART & PCM interfaces for BT function. Table 23: Pin Definition of WLAN and BT Interfaces Pin Name Pin No.
  • Page 64 Automotive Module Series AG521R-NA QuecOpen Hardware Design GPIOs. BT_UART_CTS BT UART clear to send PCM_SYNC PCM data frame sync PCM_CLK PCM data bit clock PCM_IN PCM data input PCM_OUT PCM data output Others interfaces WLAN power supply enable control WLAN_PWR_EN2 WLAN power supply enable control WLAN_PWR_EN1 1.8 V power domain.
  • Page 65 Automotive Module Series AG521R-NA QuecOpen Hardware Design VDD_EXT 100K 100K PCIE_CLKREQ PCIE_CLKREQ_N PCIE_WAKE PCIE_WAKE PCIE_RST PCIE_RST PCIE_REFCLK_P PCIE_REFCLKP PCIE_REFCLKM PCIE_REFCLK_M 100 nF PCIE_TX_M PCIE_RXM 100 nF PCIE_TX_P PCIE_RXP 100 nF PCIE_RX_M PCIE_TXM 100 nF PCIE_RX_P PCIE_TXP COEX_UART_ RXD COEX_UART_ TXD COEX_UART_ TXD COEX_UART_ RXD BT_UART_TXD...

  • Page 66: Adc Interfaces

    Automotive Module Series AG521R-NA QuecOpen Hardware Design The following principles of PCIe interface design should be complied with, so as to meet PCIe Gen2 specifications. ⚫ It is important to route the PCIe signal traces as differential pairs with ground surrounded. And the differential impedance is 95 Ω...

  • Page 67: Usb_Boot Interface

    Automotive Module Series AG521R-NA QuecOpen Hardware Design ADC Sample Rate NOTES The input voltage for each ADC interface must not exceed its corresponding voltage range. It is prohibited to supply any voltage to ADC pins when VBAT is removed. It is recommended to use resistor divider circuit for ADC application. 3.18.
  • Page 68 Automotive Module Series AG521R-NA QuecOpen Hardware Design Table 27: Pin Definition of GPIOs Pin Name Pin No. Description Comment GPIO1 GPIO2 GPIO3 GPIO4 1.8 V power domain. General-purpose input/output unused, keep them open. GPIO5 GPIO6 GPIO7 GPIO8 AG521R-NA_QuecOpen_Hardware_Design 67 / 92...

  • Page 69: Antenna Interfaces

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Antenna Interfaces The module includes one main antenna interface (ANT_MAIN) and one Rx-diversity antenna interface (ANT_DIV) which is used to resist the fall of signals caused by high speed movement and multipath effect. The antenna ports have an impedance of 50 Ω.

  • Page 70: Reference Design Of Rf Antenna Interfaces

    Automotive Module Series AG521R-NA QuecOpen Hardware Design LTE-FDD B14 788-798 758-768 LTE-FDD B17 704-716 734-746 LTE-FDD B26 814-849 859~894 LTE-FDD B5 824~849 869~894 LTE-FDD B30 2350-2360 LTE-FDD B7 2500~2570 2620~2690 LTE-FDD B71 663-698 617-652 LTE-FDD B29 717-728 NOTE LTE-FDD B29, B30 and B32 support Rx only. 4.1.3.

  • Page 71: Reference Design Of Rf Layout

    Automotive Module Series AG521R-NA QuecOpen Hardware Design ANT_DIV function is enabled by default. AT+QCFG="diversity",0 command can be used to disable receive diversity. See document [3] for details of the command. 4.1.4. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’...
  • Page 72 Automotive Module Series AG521R-NA QuecOpen Hardware Design Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, the following principles should be complied with in RF layout design: ⚫...

  • Page 73: Antenna Installation

    Automotive Module Series AG521R-NA QuecOpen Hardware Design 4.2. Antenna Installation 4.2.1. Antenna Requirements The following table shows the requirements on the main antenna and the Rx-diversity antenna. Table 30: Antenna Requirements Type Requirements VSWR: ≤ 2 Efficiency: > 30% Max input power: 50 W Input impedance: 50 Ω...
  • Page 74 Automotive Module Series AG521R-NA QuecOpen Hardware Design Figure 36: Description of the HFM Connector For more details, visit https://www.rosenbergerap.com. AG521R-NA_QuecOpen_Hardware_Design 73 / 92...

  • Page 75: Reliability, Radio And Electrical Characteristics

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Reliability, Radio and Electrical Characteristics 5.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 31: Absolute Maximum Ratings Parameter Min.

  • Page 76: Operation And Storage Temperatures

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Parameter Description Conditions Min. Typ. Max. Unit VBAT_RF the minimum and maximum values. USB connection USB_VBUS 5.25 detection 5.3. Operation and Storage Temperatures Table 33: Operation and Storage Temperatures Parameter Min. Typ. Max. Unit Operation Temperature Range º...

  • Page 77: Rf Output Power

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Table 34: Module Current Consumption (25 ° C, 3.8 V Power Supply) Description Conditions Typ. Unit OFF state Power down 0.021 AT+CFUN=0 (USB disconnected) 1.144 LTE-FDD PF = 32 (USB disconnected) 4.19 LTE-FDD PF = 64 (USB disconnected) 2.72 Sleep state LTE-FDD PF = 64 (USB suspend)

  • Page 78: Rf Receiving Sensitivity

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Table 35: RF Output Power Frequency Max. Min. LTE-FDD B2 23 dBm ± 2 dB <- 39 dBm LTE-FDD B4 23 dBm ± 2 dB <- 39 dBm LTE-FDD B5 23 dBm ± 2 dB <- 39 dBm LTE-FDD B7 23 dBm ±...

  • Page 79: Electrostatic Discharge

    Automotive Module Series AG521R-NA QuecOpen Hardware Design LTE-TDD B14 (10 MHz) -99.6 -100 -102.8 -93.3 dBm LTE-TDD B25 (10 MHz) -98.8 -102 -92.8 dBm LTE-TDD B26 (10 MHz) -100 -100.3 -103 -93.8 dBm LTE-TDD B29 (10 MHz) -98.5 -101 -102 -93.3 dBm LTE-TDD B30 (10 MHz) -97.7...
  • Page 80 Automotive Module Series AG521R-NA QuecOpen Hardware Design ⚫ Do not place components on the opposite side of the PCB area where the module is mounted, in order to facilitate adding of heatsink when necessary. ⚫ Do not apply solder mask on the opposite side of the PCB area where the module is mounted, so as to ensure better heat dissipation performance.
  • Page 81 Automotive Module Series AG521R-NA QuecOpen Hardware Design NOTES For better performance, the maximum temperature of the internal BB chip should be kept below 105 ° C. When the maximum temperature of the BB chip reaches or exceeds 105 ° C, the module works normal but provides reduced performance (such as RF output power and data rate).

  • Page 82: Mechanical Dimensions

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ± 0.05 mm unless otherwise specified. 6.1. Mechanical Dimensions Figure 39: Module Top and Side Dimensions AG521R-NA_QuecOpen_Hardware_Design 81 / 92...
  • Page 83 Automotive Module Series AG521R-NA QuecOpen Hardware Design Figure 40: Module Bottom Dimensions (Top View) NOTE The package warpage level of the module conforms to JEITA ED-7306 standard. AG521R-NA_QuecOpen_Hardware_Design 82 / 92...

  • Page 84: Recommended Footprint

    Automotive Module Series AG521R-NA QuecOpen Hardware Design 6.2. Recommended Footprint Figure 41: Recommended Footprint (Top View) NOTE For convenient maintenance of the module, please keep about 3 mm between the module and other components on the motherboard. AG521R-NA_QuecOpen_Hardware_Design 83 / 92...

  • Page 85: Top And Bottom Views

    AG521R-NA QuecOpen Hardware Design 6.3. Top and Bottom Views Figure 42: Top View of the Module Figure 43: Bottom View of the Module NOTE These are renderings of the module. For authentic appearance, see the module received from Quectel. AG521R-NA_QuecOpen_Hardware_Design 84 / 92...

  • Page 86: Storage, Manufacturing And Packaging

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Storage, Manufacturing and Packaging 7.1. Storage The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 ± 5 ° C and the relative humidity should be 35–60 %.

  • Page 87: Manufacturing And Soldering

    Automotive Module Series AG521R-NA QuecOpen Hardware Design This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. 2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules to the air for a long time.

  • Page 88: Packaging

    Automotive Module Series AG521R-NA QuecOpen Hardware Design Factor Recommendation Soak Zone Max slope 1–3 ° C/s Soak time (between A and B: 150° C and 200° C) 70–120 s Reflow Zone Max slope 2–3 ° C/s Reflow time (D: over 220° C) 45–70 s Max temperature 238–246 °...
  • Page 89 Automotive Module Series AG521R-NA QuecOpen Hardware Design Figure 45: Tape Specifications Figure 46: Reel Specifications AG521R-NA_QuecOpen_Hardware_Design 88 / 92...

  • Page 90: Appendix A References

    EVB User Guide for Automotive Modules Quectel_AG52xR_Series_QuecOpen_Developer_Guide AG52xR Series QuecOpen Developer Guide Quectel_AG52xR_Series _AT_Commands_Manual AG52xR Series AT Commands Manual Quectel_RF_Layout_Application_Note RF Layout Application Note Thermal Design Guide for Quectel LTE (LTE Quectel_LTE_Module_Thermal_Design_Guide Standard/LTE-A/Automotive) modules Quectel Module Secondary SMT Application Quectel_Module_Secondary_SMT_Application_Note Note Quectel_AG52xR_Series_QuecOpen_Reference_Design...
  • Page 91 Automotive Module Series AG521R-NA QuecOpen Hardware Design DC-HSPA+ Dual-carrier High Speed Packet Access DFOTA Delta Firmware Upgrade Over The Air Downlink Data Terminal Ready Discontinuous Transmission Enhanced Full Rate Electrostatic Discharge EVDO Evolution-Data Optimized Frequency Division Duplex Full Rate GLObalnaya NAvigatsionnaya Sputnikovaya Sistema, the Russian Global GLONASS Navigation Satellite System GMSK...
  • Page 92 Automotive Module Series AG521R-NA QuecOpen Hardware Design Mobile Station (GSM engine) Mobile Terminated Password Authentication Protocol Printed Circuit Board Protocol Data Unit Point-to-Point Protocol Peak Pulse Power Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying Radio Frequency RHCP Right Hand Circularly Polarized Receive SIMO Single Input Multiple Output...
  • Page 93 Automotive Module Series AG521R-NA QuecOpen Hardware Design Maximum Input High Level Voltage Value Minimum Input High Level Voltage Value Maximum Input Low Level Voltage Value Minimum Input Low Level Voltage Value Absolute Maximum Input Voltage Value Absolute Minimum Input Voltage Value Maximum Output High Level Voltage Value Minimum Output High Level Voltage Value Maximum Output Low Level Voltage Value...

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