Adc Interfaces - Quectel LTE-A Series Hardware Design

Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. Please refer to
document [3] for details about AT+QDAI command.
The following figure shows a reference design of PCM interface with an external codec IC.
PCM_CLK
PCM_SYNC
PCM_OUT
PCM_IN
I2C_SCL
I2C_SDA
Module
VDD_EXT
Figure 29: Reference Circuit of PCM Application with Audio Codec
NOTES
1. It is recommended to reserve an RC (R=22Ω, C=22pF) circuit on the PCM lines, especially for
PCM_CLK.
2. EG18 works as a master device pertaining to I2C interface.

3.13. ADC Interfaces

The module provides two Analog-to-Digital Converters (ADC) interfaces. AT+QADC=0 command can be
executed to read the voltage value on ADC0. AT+QADC=1 command can be executed to read the
voltage value on ADC1 pin. For more details about these AT+QADC commands, please refer to
document [3].
EG18_Hardware_Design
MICBIAS
INP
BCLK
INN
LRCK
DAC
ADC
LOUTP
SCL
SDA
LOUTN
Codec
LTE-A Module Series
EG18 Hardware Design
57 / 104