Linear Flash; Xilinx Xc95144Xl Cpld - Xilinx ML405 User Manual

Evaluation platform

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Chapter 1: ML405 Evaluation Platform

19. Linear Flash

Two 32-Mb linear flash devices (Micron MT28F320J3RG-11 ET) are installed on the board

for a total of 8 MB of flash memory. These flash memory devices are Intel StrataFlash

compatible. This memory provides non-volatile storage of data, software, or bitstreams.

Each flash device is 16 bits wide and together forms a 32-bit data bus that is shared with

SRAM. Each flash device is 16 bits wide, and the two devices together form a 32-bit data

bus that is shared with SRAM.In conjunction with a CPLD, the flash memory can also be

used to program the FPGA.

Note:

is designed to be asserted at power-on or upon system reset.

A Xilinx XC95144XL CPLD is connected to the flash memory and the FPGA configuration

signals. This supports applications where flash memory programs the FPGA. The CPLD is

programmed from the main JTAG chain of the board. The CPLD is wired so that it can

support master or slave configuration in serial or parallel (SelectMAP) modes. For FPGA

configuration via the CPLD and flash, the configuration selector switch (SW12) must be set

to the CPLD Flash position. See the

information.

The reset for the AC97 Codec is shared with the reset signal for the flash memory chips and

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"Configuration Options," page 33

UG210 (v1.5.1) March 10, 2008

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ML405 Evaluation Platform

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