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Chapter 1: ML405 Evaluation Platform
Single-Ended Expansion I/O Connectors
Header J6 contains 32 single-ended signal connections to the FPGA I/Os. This permits the
signals on this connector to carry high-speed single-ended data. All single-ended signals
on connector J6 are matched length traces. The V
3.3V by setting jumpers J15, J16, and J23 .
connections on this expansion I/O connector.
Table 1-9: Expansion I/O Single-Ended Connections (J6)
18
J6 Pin
Schematic Net Name
2
HDR1_28
4
HDR1_42
6
HDR1_36
8
HDR1_2
10
HDR1_52
12
HDR1_32
14
HDR1_26
16
HDR1_12
18
HDR1_50
20
HDR1_38
22
HDR1_40
24
HDR1_22
26
HDR1_10
28
HDR1_60
30
HDR1_24
32
HDR1_4
34
HDR1_30
36
HDR1_6
38
HDR1_34
40
HDR1_18
42
HDR1_16
44
HDR1_54
46
HDR1_56
48
HDR1_46
50
HDR1_20
52
HDR1_14
54
HDR1_48
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of these signals can be set to 2.5V or
CCIO
Table 1-9
summarizes the single-ended
FPGA Pin
Y16
R20
W24
T20
R21
U20
Y15
T22
P24
U17
T17
R23
T24
T23
U24
V23
V22
W23
V24
Y23
AD20
AD21
AC21
AD19
Y17
AD18
AA17
ML405 Evaluation Platform
UG210 (v1.5.1) March 10, 2008
R
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