Xilinx ML405 User Manual page 2

Evaluation platform
Hide thumbs Also See for ML405:
Table of Contents

Advertisement

Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development
of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the
Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,
without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves
the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors
contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with
technical support or assistance that may be provided to you in connection with the Information.
THE DOCUMENTATION IS DISCLOSED TO YOU "AS-IS" WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER
WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY
RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL
DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.
© 2006–2008 Xilinx, Inc. All rights reserved.
XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a
trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
Revision History
The following table shows the revision history for this document.
Date
Version
06/23/06
1.0
06/30/06
1.0.1
01/31/07
1.1
03/21/07
1.2
05/02/07
1.3
06/28/07
1.4
08/13/07
1.5
03/10/08
1.5.1
ML405 Evaluation Platform
Initial Xilinx release.
Release to Web.
Updated jumper information for
Updated
Table 1-19, page 31
Added
Appendix A, "Board Revisions"
Updated
Table 1-19, page 31
Corrected J5 pinout for HDR2_8 in
Minor edits to
Table A-1, page
www.xilinx.com
R
Revision
2.5V and 3.3V operation (
(see table notes).
and information for RoHS-compliant boards.
for XAUI/SRIO support.
Table 1-8, page 17
(U19).
35.
Table 1-1, page
12).
UG210 (v1.5.1) March 10, 2008

Advertisement

Table of Contents
loading

Table of Contents