Expansion Headers - Xilinx ML405 User Manual

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10. Expansion Headers

The board contains expansion headers (U3, U4, U5, and U6) for easy expansion or
adaptation of the board for other applications. The expansion connectors use standard
0.1-inch headers. The expansion connectors contain connections to single-ended and
differential FPGA I/Os, ground, 2.5V/3.3V/5V power, JTAG chain, and the IIC bus. All
signals on connectors U5 and U6 have matched length traces that are matched to each
other.
Differential Expansion I/O Connectors
Header J5 contains 16 pairs of differential signal connections to the FPGA I/Os. This
permits the signals on this connector to carry high-speed differential signals, such as LVDS
data. All differential signals are routed with 100Ω differential trace impedance. Matched
length traces are used across all differential signals on U5. Consequently, these signals
connect to the FPGA I/O and they can be used as independent single-ended nets. The
V
Table 1-8
Table 1-8: Expansion I/O Differential Connections (J5)
ML405 Evaluation Platform
UG210 (v1.5.1) March 10, 2008
of these signals can be set to 2.5V or 3.3V by setting jumpers J15, J16, and J23 .
CCIO
summarizes the differential connections on this expansion I/O connector.
J5 Differential Pin Pair
Pos Neg
4 2
8 6
12 10
16 14
20 18
24 22
28 26
32 30
36 34
40 38
44 42
48 46
52 50
56 54
60 58
64 62
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Schematic Net Name
Pos Neg
HDR2_4 HDR2_2
HDR2_28 HDR2_26
HDR2_20 HDR2_18
HDR2_12 HDR2_10
HDR2_8 HDR2_6
HDR2_60 HDR2_58
HDR2_56 HDR2_54
HDR2_52 HDR2_50
HDR2_36 HDR2_34
HDR2_16 HDR2_14
HDR2_64 HDR2_62
HDR2_48 HDR2_46
HDR2_24 HDR2_22
HDR2_44 HDR2_42
HDR2_32 HDR2_30
HDR2_40 HDR2_38
Detailed Description
FPGA Pin
Pos Neg
Y22 AA22
AC19 AC18
AA18 Y18
AD16 AC16
U19 T18
AB20 AB19
W20 W19
W18 V18
AB22 AB21
W21 Y20
AB24 AC24
AD24 AD23
AA24 AA23
AA20 AA19
V21 U21
AC23 AC22
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