Addressing; I/O Module Data - WAGO I/O SYSTEM 750 750-833 Manual

3.4.6 Addressing

3.4.6.1

I/O Module Data

The CPU has direct access to the bus terminal data through absolute
addresses. Addressing is organized word-by-word and begins with the address
0 both with inputs and outputs. The corresponding addresses for bits, bytes
and double words (dword) are derived from the word addresses.
The structure of the process image is described in chapter 3.4., "Process
Image" is done in this structure.
Input data
Output data
WAGO-I/O-SYSTEM 750
Bus System
Data Size
Bit 0.0
...
0.7
Byte 0
Word 0
Dword
Data Size
Bit 0.0
...
0.7
Byte 0
Word 0
Dword
Programmable Field Bus Controller 750-833
Addresses up to SW 02
0.8 1.0 1.8
... ... ...
0.15 1.7 1.15
1 2 3
1
0
Addresses from SW 03
0.8 1.0 1.8
... ... ...
0.15 1.7 1.15
1 2 3
1
0
%IW0 word oriented data
|
%IW
n
%I bit oriented data
n+1
|
%I
n+m
%QW0 word oriented data
|
%QW
n
%Q bit oriented data
n+1
|
%Q
n+m
Process Image
... 62.0 62.8 63.0
... ...
62.7 62.15 63.7
... 124 125 126
... 62
... 31
... 120.0 120.8 121.0
... ...
120.7 120.15 121.7
... 240 241 242
... 120
... 60
• 67
63.8
... ...
63.15
127
63
121.8
... ...
121.15
243
121