Clock Configuration - Motorola Digital DNA MSC8101 Technical Data Manual

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Clock Configuration

2.6 Clock Configuration
The following sections provide a general description of clock configuration.
2.6.1 Valid Clock Modes
Table 2-6 shows the maximum frequency values for each rated core frequency (250, 275, or 300 MHz).
The user must ensure that maximum frequency values are not exceeded.
Core Frequency
CPM Frequency (CPMCLK)
Bus Frequency (BCLK)
Serial Communication Controller Clock Frequency (SCLK)
Baud Rate Generator Clock Frequency (BRGCLK)
External Clock Output Frequency (CLKOUT)
Six bit values map the MSC8101 clocks to one of the valid configuration mode options. Each option
determines the
values are derived from three dedicated input pins (
configuration word (MODCK_H). To configure the SPLL pre-division factor, SPLL multiplication
factor, and the frequencies for the SC140 core, SCC clocks, CPM parallel I/O ports, and system buses,
the
power-on reset (internal
PORESET
The following factors are configured:
• SPLL pre-division factor (SPLL PDF)
• SPLL multiplication factor (SPLL MF)
• Bus post-division factor (Bus DF)
The SCC division factor (SCC DF) is fixed at 4 and the CPM division factor (CPM DF) is fixed at 2. The
BRG division factor (BRG DF) is configured through the System Clock Control Register (SCCR) and
can be 4, 16 (default after reset), 64, or 256.
Note:
2.6.2 Clocks Programming Model
This section describes the clock registers in detail. The registers discussed are as follows:
• System Clock Control Register (SCCR)
• System Clock Mode Register (SCMR)
2-4
Characteristic
CLKIN
, SC140 core, system bus, SCC clock, CPM, and
MODCK[1–3]
pins are sampled and combined with the MODCK_H values when the internal
PORESET
signal is deasserted.
Refer to AN2288/D Clock Mode Selection for MSC8101 Mask Set 2K42A for details on clock
configuration.
Table 2-6. Maximum Frequencies
MODCK[1–3]
) is deasserted. Clock configuration changes only when the internal
Maximum Frequency in MHz
250
275
125
137.5
50
68.75
62.5
68.75
62.5
68.75
50
68.75
CLKOUT
frequencies. The six bit
) and three bits from the reset
300
150
75
75
75
75

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