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Name
General-
Peripheral Controller:
Purpose
Dedicated I/O
I/O
Protocol
PC7
SI2: L1ST1
FCC1: CTS
HDLC serial , HDLC nibble ,
and transparent
FCC1: TXADDR2
UTOPIA master
FCC1: TXADDR2
UTOPIA slave
FCC1: TXCLAV1
UTOPIA multi-PHY master,
direct polling
Communications Processor Module (CPM) Ports
Table 1-5. Port C Signals (Continued)
Dedicated
I/O Data
Direction
Output
Serial Interface 2: Strobe 1
In the time-slot assigner supported by SI2. The MSC8101
time-slot assigner supports up to four strobe outputs that can
be asserted on a bit or byte basis. The strobe outputs are
useful for interfacing to other devices that do not support the
multiplexed interface or for enabling/disabling three-state I/O
buffers in a multiple-transmitter architecture. These strobes
can also generate output wave forms for such applications as
stepper-motor control.
Input
FCC1: Clear To Send
In the standard modem interface signals supported by FCC1
(RTS, CTS, and CD). CTS is asynchronous with the data.
Output
FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 2
In the ATM UTOPIA master interface supported by FCC1, this
is transmit address bit 2.
Input
FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 2
In the ATM UTOPIA slave interface supported by FCC1 using
multiplexed polling, this is transmit address bit 2.
Input
FCC1: UTOPIA Multi-PHY Master Transmit Cell Available
1 Direct Polling
In the ATM UTOPIA master interface supported by FCC1
using direct polling, TXCLAV1 is asserted by an external
UTOPIA slave PHY to indicate that it can accept one
complete ATM cell.
Description
1-39
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