Table of Contents
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Index
signals, external Bus UPM Wait
SIU inputs 2-13
SIU outputs 2-13
Spare Pins signal 1-46
SPLL MF 2-4
SPLL multiplication factor 2-4
SPLL PDF 2-4
SRAM iii
SRESET 1-7
storage temperature 2-1
supply voltage 2-1
System Clock Control Register (SCCR) 2-5
System Clock Mode Register (SCMR) 2-6
Index-4
Bus UPM General-Purpose Line 4
(PGPL4) 1-17
Bus UPM General-Purpose Line 5
(PGPL5) 1-17
Data Bus Bit 48–51 (D[48–51]) 1-10
Data Bus Bit 52 (D52) 1-11
Data Bus Bit 53 (D53) 1-11
Data Bus Bit 54 (D54) 1-11
Data Bus Bit 55 (D55) 1-11
Data Bus Bit 56 (D56) 1-12
Data Bus Bit 57 (D57) 1-12
Data Bus Bit 58 (D58) 1-12
Data Bus Bit 59 (D59) 1-12
Data Bus Bit 60 (D60) 1-12
Data Bus Bit 61–63 (D[61–63]) 1-12
Data Bus Bits 32–47 (D[32–47] ) 1-10
Data Bus Busy (DBB) 1-10
Data Bus Grant (DBG) 1-10
Global (GBL) 1-8
GPCM TA (PGTA) 1-17
Host Address Line 0 (HA0) 1-10
Host Chip Select (HCS) 1-11
Host Data (H[0–15]) 1-10
Host Read Strobe (HRD) 1-11
Host Read Write Select 1-11
Interrupt Request 1 (IRQ1) 1-13
Interrupt Request 2 (IRQ2) 1-9
Interrupt Request 3 (IRQ3) 1-9
Interrupt Request 4 (IRQ4) 1-14
Interrupt Request 5 (IRQ5) 1-9
Interrupt Request 6 (IRQ6) 1-14
Interrupt Request 7 (IRQ7) 1-14
Spare Pins (SPARE1, 5) 1-46
(PUPMWAIT) 1-17
T
TAP timing diagram 2-23
target applications iv
TDM signal diagram 2-21
Test Clock (TCK) input timing diagram 2-23
thermal
design considerations 4-1
thermal characteristics 2-2
timing
interrupt 2-9
mode select 2-9
Reset 2-9
Stop 2-9
timings
AC 2-7
EE pins 2-22
Transfer Acknowledge (TA) 1-14
Transfer Error Acknowledge (TEA) 1-15
Transmit Host Request (HTRQ) 1-11
U
UPM Byte Select (PBS) 1-16
,
1-13
,
,
1-10
1-13
,
1-14
,
1-15
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