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Communications Processor Module (CPM) Ports
General-
Purpose
1-28
Table 1-4. Port B Signals (Continued)
Name
Peripheral Controller:
Dedicated I/O
I/O
Protocol
PB28
FCC2: RTS
HDLC serial , HDLC nibble ,
and transparent
FCC2: RX_ER
MII
SCC2: RTS, TENA
SI2 TDMB2: L1TSYNC
TDM serial
PB27
FCC2: COL
MII
SI2 TDMC2: L1TXD
TDM serial
PB26
FCC2: CRS
MII
SI2 TDMC2: L1RXD
TDM serial
Dedicated
I/O Data
Direction
Output
FCC2: Request to Send
One of the standard modem interface signals supported by
FCC2 (RTS, CTS, and CD). RTS is asynchronous with the
data. RTS is typically used in conjunction with CD. The
MSC8101 FCC2 transmitter requests the receiver to send
data by asserting RTS low. The request is accepted when
CTS is returned low.
Input
FCC2: Media Independent Interface Receive Error
In the MII interface supported by FCC2, RX_ER is asserted
by an external fast Ethernet PHY. This signal indicates a
receive error, which often indicates bad wiring.
Output
SCC2: Request to Send, Transmit Enable
Typically used in conjunction with CD supported by SCC2.
The MSC8101 SCC2 transmitter requests the receiver to
send data by asserting RTS low. The request is accepted
when CTS is returned low. TENA is the signal used in
Ethernet mode.
Input
Time-Division Multiplexing B2: Layer 1 Transmit
Synchronization
In the TDMB2 interface supported by SI2, this is the
synchronizing signal for the transmit channel. See the Serial
Interface with Time-Slot Assigner chapter in the MSC8101
Technical Reference manual.
Input
FCC2: Media Independent Interface Collision Detect
In the MII interface supported by FCC2. COL is asserted by
an external fast Ethernet PHY.
Output
Time-Division Multiplexing C2: Layer 1 Transmit Data
In the TDMC2 interface supported by SI2. L1TXD supports
serial mode. TDMC2 transmits serial data out of L1TXD.
Input
FCC2: Media Independent Interface Carrier Sense Input
In the MII interface, CRS is asserted by an external fast
Ethernet PHY. This signal indicates activity on the cable.
Input
Time-Division Multiplexing C2: Layer 1 Receive Data
In the TDMC2 interface supported by SI2. L1RXD supports
serial mode. TDMC2 receives serial data from L1RXD.
Description
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