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Name
General-
Peripheral Controller:
Purpose
Dedicated I/O
I/O
Protocol
PD19
FCC1: TXADDR4
UTOPIA master
FCC1: TXADDR4
UTOPIA slave
FCC1: TXCLAV3
UTOPIA multi-PHY master,
direct polling
BRG1O
SPI: SPISEL
Communications Processor Module (CPM) Ports
Table 1-6. Port D Signals (Continued)
Dedicated
I/O Data
Direction
Output
FCC1: Multi-PHY Master Transmit Address Bit 4
Multiplexed Polling
In the ATM UTOPIA master interface supported by FCC1
using multiplexed polling, this is transmit address bit 4.
Input
FCC1: UTOPIA Slave Transmit Address Bit 4
In the ATM UTOPIA slave interface supported by FCC1
using multiplexed polling, this is transmit address bit 4.
Input
FCC1: UTOPIA Multi-PHY master Transmit Cell
Available 3 Direct Polling
In the ATM UTOPIA master interface supported by FCC1
using direct polling, TXCLAV3 is asserted by an external
UTOPIA slave PHY to indicate that it can accept one
complete ATM cell.
Output
Baud Rate Generator 1 Output
The CPM supports up to 8 BRGs. The BRGs can be used
internally by the bank-of-clocks selection logic and/or
provide an output to one of the 8 BRG pins. BRG1O can be
the internal input to the SIU timers. When CLK5 is selected
(see PC27 above), it is the source for BRG1O which is the
default input for the SIU timers. See the System Interface
Unit (SIU) chapter in the MSC8101 Technical Reference
manual for additional information. If CLK5 is not enabled,
BRG1O uses an internal input. If TMCLK is enabled (see
PC26 above), the BRG1O input to the SIU timers is
disabled.
Input
SPI: Select
The SPI interface comprises four signals: master out slave
in (SPIMOSI), master in slave out (SPIMISO), clock
(SPICLK) and select (SPISEL). The SPI can be configured
as a slave or master in single- or multiple-master
environments. SPISEL is the enable input to the SPI slave.
In a multimaster environment, SPISEL (always an input)
detects an error when more than one master is operating.
SPI masters must output a slave select signal to enable SPI
slave devices by using a separate general-purpose I/O
signal. Assertion of an SPI SPISEL while it is master causes
an error.
Description
1-43
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