Motorola Digital DNA MSC8101 Technical Data Manual page 68

AC Timings
Figure 2-12 shows Host DMA read timing.
Figure 2-13 shows Host DMA write timing.
2-18
HREQ
(Output)
64
44a
HACK or
RX[0–3]
HWR, HDS,
Read
HRD (Input)
50
49
HD[0–15]
(Output)
Figure 2-12. Host DMA Read Timing Diagram
HREQ
(Output)
64
45
HACK or
TX[0–3]
Write
HWR, HDS,
HRD (Input)
47
HD[0–15]
(Output)
Figure 2-13. Host DMA Write Timing Diagram
63
44b
51
52
Data
Valid
63
46
48
Data
Valid