Motorola Digital DNA MSC8101 Technical Data Manual page 40

Communications Processor Module (CPM) Ports
General-
Purpose
1-36
Table 1-5. Port C Signals (Continued)
Name
Peripheral Controller:
Dedicated I/O
I/O Protocol
PC23 CLK9
DMA: DACK1
EXT2
PC22 SI1: L1ST1
CLK10
DMA: DREQ1
Dedicated
I/O Data
Direction
Input Clock 9
The CPM supports up to 10 clock input pins. The clocks are
sent to the bank-of-clocks selection logic, where they can be
routed to the controllers.
Output DMA: Data Acknowledge 1
DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU
DMA. DONE1 and DRACK1 are signals on the same pin and
therefore cannot be used simultaneously. There are two sets
of DMA pins associated with the PIO ports.
Input External Request 2
External request input line 2 asserts an internal request to the
CPM processor. The signal can be programmed as level- or
edge-sensitive, and also has programmable priority. Refer to
the RISC Controller Configuration Register (RCCR)
description in the Chapter 17 of the MSC8101 Reference
Manual for programming information. There are no current
microcode applications for this request line. It is reserved for
future development.
Output Serial Interface 1: Layer 1 Strobe 1
In the time-slot assigner supported by SI1. The MSC8101
time-slot assigner supports up to four strobe outputs that can
be asserted on a bit or byte basis. The strobe outputs are
useful for interfacing to other devices that do not support the
multiplexed interface or for enabling/disabling three-state I/O
buffers in a multiple-transmitter architecture. These strobes
can also generate output wave forms for such applications as
stepper-motor control.
Input Clock 10
The CPM supports up to 10 clock input pins. The clocks are
sent to the bank-of-clocks selection logic, where they can be
routed to the controllers.
Input/ DMA: Request 1
Output DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU
DMA. DONE1 and DRACK1 are signals on the same pin and
therefore cannot be used simultaneously. There are two sets
of DMA pins associated with the PIO ports.
Description