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N
networking capabilities iv
Non-Maskable Interrupt (NMI) 1-15
Non-Maskable Interrupt Output(NMI_OUT) 1-15
non-multiplexed bus timings
read 2-17
write 2-18
O
outputs
SIU 2-13
P
package iii
FC-PBGA description 3-32
pinout
bottom view 3-3
top view 3-2
PIO, timer, and DMA signal diagram 2-21
PLLs iii
PORESET 1-7
power 1-4
power considerations 4-2
power consumption iii
power dissipation 4-3
power-on reset flow 2-9
PowerPC bus interface iii
process technology iii
product documentation iv
programmable memory controller iii
R
Receive Host Request (HRRQ) 1-12
reset
actions 2-9
determine the PLL locking mode 2-9
external configuration signals
Boot Mode 2-9
EONCE Event Bit 0 2-9
Host Port Enable 2-9
Reset Configuration 2-9
hard reset 2-9
hardware reset configuration 2-9
host reset configuration 2-9
PORESET 2-10
power-on reset flow 2-9
program reset configuration word via the Host
port 2-10
reset causes 2-8
reset sources 2-8
RSTCONF 2-11
soft reset 2-9
RSTCONF 1-7
S
SC140 core iii
SCC/SMC/SPI/I2C external clock diagram 2-21
SCC/SMC/SPI/I2C internal clock diagram 2-21
SDRAM DQM (PSDDQM[0–7]) 1-16
signal groupings 1-1
signals 1-1
EE 2-22
external 1-2
JTAG 2-22
memory controller
tick spacing 2-12
multiplexed 1-1
signals, external
Address Acknowledge (AACK) 1-10
Address Bus (A[0–31]) 1-8
Address Bus Busy (ABB) 1-9
Address Retry (ARTRY) 1-10
Burst Address 29 (BADDR29) 1-9
Burst Address 30 (BADDR30) 1-9
Bus Grant 1-9
Bus Grant (BG) 1-9
Bus Output Enable (POE) 1-17
Bus Parity Byte Select (PPBS) 1-17
Bus request signal (BR) 1-9
Bus SDRAM A10 (PSDA10) 1-16
Bus SDRAM Address Multiplexer
(PSDAMUX) 1-17
Bus SDRAM CAS (PSDCAS) 1-17
Bus SDRAM RAS (PSDRAS) 1-17
Bus SDRAM Write Enable (PSDWE) 1-16
Bus Transfer Start (TS) 1-10
Bus UPM General Purpose Line 1
(PGPL1) 1-16
Bus UPM General-Purpose Line 0
(PGPL0) 1-16
Bus UPM General-Purpose Line 2
(PGPL2) 1-17
Bus UPM General-Purpose Line 3
(PGPL3) 1-17
Bus UPM General-Purpose Line 4 1-17
Index
Index-3
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