Motorola Digital DNA MSC8101 Technical Data Manual page 36

Communications Processor Module (CPM) Ports
1.7.3 Port C Signals
General-
Purpose
1-32
Name
Peripheral Controller:
Dedicated I/O
I/O Protocol
PC31 BRG1O
CLK1
TIMER1/2: TGATE1
PC30 BRG2O
CLK2
Timer1: TOUT1
EXT1
Table 1-5. Port C Signals
Dedicated
I/O Data
Direction
Output Baud-Rate Generator 1 Output
The CPM supports up to 8 BRGs. The BRGs can be used
internally by the bank-of-clocks selection logic and/or provide
an output to one of the 8 BRG pins. BRG1O can be the
internal input to the SIU timers. When CLK5 is selected (see
PC27 below), it is the source for BRG1O which is the default
input for the SIU timers. See the System Interface Unit (SIU)
chapter in the MSC8101 Technical Reference manual for
additional information. If CLK5 is not enabled, BRG1O uses
an internal input. If TMCLK is enabled (see PC26 below), the
BRG1O input to the SIU timers is disabled.
Input Clock 1
The CPM supports up to 10 clock input pins. The clocks are
sent to the bank-of-clocks selection logic, where they can be
routed to the controllers.
Input Timer 1/2: Timer Gate 1
The timers can be gated/restarted by an external gate signal.
There are two gate signals: TGATE1 controls timer 1 and/or 2
and TGATE2 controls timer 3 and/or 4.
Output Baud-Rate Generator 2 Output
The CPM supports up to 8 BRGs. The BRGs can be used
internally by the bank-of-clocks selection logic and/or provide
an output to one of the 8 BRG pins.
Input Clock 2
The CPM supports up to 10 clock input pins. The clocks are
sent to the bank-of-clocks selection logic, where they can be
routed to the controllers.
Output Timer 1: Timer Out 1
The timers (Timer[1–4]) can output a signal on a timer output
(TOUT[1–4]) when the reference value is reached. This signal
can be an active-low pulse or a toggle of the current output.
The output can also connect internally to the input of another
timer, resulting in a 32-bit timer.
Input External Request 1
External request input line 1 asserts an internal request to the
CPM processor. The signal can be programmed as level- or
edge-sensitive, and also has programmable priority. Refer to
the RISC Controller Configuration Register (RCCR)
description in the Chapter 17 of the MSC8101 Reference
Manual for programming information. There are no current
microcode applications for this request line. It is reserved for
future development.
Description