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Communications Processor Module (CPM) Ports
General-
Purpose
1-26
Table 1-3. Port A Signals (Continued)
Name
Peripheral Controller:
Dedicated Signal
I/O
Protocol
PA8
SMC2: SMRXD
SI1 TDMA1: L1RXD0
TDM nibble
SI1 TDMA1: L1RXD
TDM serial
PA7
SMC2: SMSYN
SI1 TDMA1: L1TSYNC
TDM nibble and TDM serial
PA6
SI1 TDMA1: L1RSYNC
TDM nibble and TDM serial
Dedicated
I/O Data
Direction
Input
SMC2: Serial Management Receive Data
Supported by SMC2. The SMC interface consists of
SMTXD, SMRXD, SMSYN, and a clock. Not all signals are
used for all applications. SMCs are full-duplex ports that
supports three protocols or modes: UART, transparent, or
general-circuit interface (GCI).
Input
Time-Division Multiplexing A1: Layer 1 Nibble Receive
Data Bit 0
In the TDMA1 interface supported by SI1. L1RXD3 is the
most significant bit. L1RXD0 is the least significant bit in
nibble mode. TDMA1 receives nibble data from
L1RXD[0–3].
Input
Time-Division Multiplexing A1: Layer 1 Serial Receive
Data
In the TDMA1 interface supported by SI1. TDMA1 receives
serial data from L1RXD.
Input
SMC2: Serial Management Synchronization
The SMC interface consists of SMTXD, SMRXD, SMSYN,
and a clock. Not all signals are used for all applications.
SMCs are full-duplex ports that supports three protocols or
modes: UART, transparent, or general-circuit interface
(GCI).
Input
Time-Division Multiplexing A1: Layer 1 Transmit
Synchronization
In the TDMA1 interface supported by SI1, this is the
synchronizing signal for the transmit channel. See the Serial
Interface with Time-Slot Assigner chapter in the MSC8101
Technical Reference manual.
Input
Time-Division Multiplexing A1: Layer 1 Receive
Synchronization.
In the TDMA1 interface supported by SI1, this is the
synchronizing signal for the receive channel.
Description
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