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Next, the MSC8101 halts until the SPLL locks. The SPLL locks according to
sampled, and to MODCK_H taken from the Reset Configuration Word. SPLL locking time is 800
reference clocks, which is the clock at the output of the SPLL Pre-divider. After the SPLL is locked, all
the clocks to the MSC8101 are enabled. If the DLLDIS bit in the reset configuration word is reset, the
DLL starts the locking process after the SPLL is locked. During PLL and DLL locking,
SRESET
SRESET
DLL is bypassed and there is no locking process, thus saving the DLL locking time. Figure 2-4 shows
the power-on reset flow.
PORESET
PORESET
Output (I/O)
Output (I/O)
2.7.3 System Bus Access Timing
2.7.3.1 Core Data Transfers
Generally, all MSC8101 bus and system output signals are driven from the rising edge of the reference
clock (REFCLK), which is
however, trigger on four points within a REFCLK cycle. Each cycle is divided by four internal ticks: T1,
T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling edge), but the
spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 2-14 shows.
are asserted.
HRESET
is released three bus clocks later. If the DLLDIS bit in the reset configuration word is set, the
1
Input
asserted for
RSTCONF is sampled for
min 16
master/slave determination
CLKIN.
Internal
HRESET
SRESET
In reset configuration mode:
reset configuration sequence
occurs in this period.
Figure 2-4. Hardware Reset Configuration Timing
DLLIN
Table 2-14. Tick Spacing for Memory Controller Signals
PLL Clock Ratio
1:2, 1:3, 1:4, 1:5, 1:6
1:2.5
1:3.5
remains asserted for another 512 BUS clocks and is then released. The
MODCK[1–3] are sampled.
MODCK_H bits are ready
for PLL.
PLL locked
2
3
PLL locks after
800 SPLLMFCLKs. DLL
locks 3073 bus clocks after
PLL is locked.
When DLL is disabled, reset
period is shortened by 3073
bus clocks.
or, if the DLL is disabled,
CLKOUT
Tick Spacing (T1 Occurs at the Rising Edge of REFCLK)
T2
1/4 REFCLK
3/10 REFCLK
4/14 REFCLK
MODCK[1–3]
HRESET
DLL locked
4
5
6
HRESET/SRESET are
extended for 512/515 bus
clocks, respectively, from PLL
and DLL Lock time.
. Memory controller signals,
T3
1/2 REFCLK
3/4 REFCLK
1/2 REFCLK
8/10 REFCLK
1/2 REFCLK
11/14 REFCLK
AC Timings
, which are
and
T4
2-11
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