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Name
General-
Peripheral Controller:
Purpose
Dedicated I/O
I/O
Protocol
PC15
SMC2: SMTXD
SCC1: CTS/CLSN
FCC1: TXADDR0
UTOPIA master
FCC1: TXADDR0
UTOPIA slave
PC14
SI1: L1ST2
SCC1: CD, RENA
FCC1: RXADDR0
UTOPIA master
FCC1: RXADDR0
UTOPIA slave
Communications Processor Module (CPM) Ports
Table 1-5. Port C Signals (Continued)
Dedicated
I/O Data
Direction
Output
SMC2: Serial Management Transmit Data
Supported by SMC2. The SMC interface consists of SMTXD,
SMRXD, SMSYN, and a clock. Not all signals are used for all
applications. SMCs are full-duplex ports that support three
protocols or modes: UART, transparent, or general-circuit
interface (GCI). See also PA9.
Input
SCC1: Clear To Send, Collision
Typically used in conjunction with RTS. The MSC8101 SCC1
transmitter sends out a request to send data signal (RTS).
The request is accepted when CTS is returned low. CLSN is
the signal used in Ethernet mode. See also PC29.
Output
FCC1: UTOPIA Master Transmit Address Bit 0
In the ATM UTOPIA master interface supported by FCC1, this
is transmit address bit 0.
Input
FCC1: UTOPIA Slave Transmit Address Bit 0
In the ATM UTOPIA slave interface supported by FCC1, this
is transmit address bit 0.
Output
Serial Interface 1: Layer 1 Strobe 2
In the time-slot assigner supported by SI1. The MSC8101
time-slot assigner supports up to four strobe outputs that can
be asserted on a bit or byte basis. The strobe outputs are
useful for interfacing to other devices that do not support the
multiplexed interface or for enabling/disabling three-state I/O
buffers in a multiple-transmitter architecture. These strobes
can also be generate output wave forms for such applications
as stepper-motor control.
Input
SCC1: Carrier Detect, Receive Enable
Typically used in conjunction with RTS supported by SCC1.
The MSC8101 SCC1 transmitter requests the receiver to
send data by asserting RTS low. The request is accepted
when CTS is returned low.
Output
FCC1: UTOPIA Multi-PHY Master Receive Address Bit 0
In the ATM UTOPIA master interface supported by FCC1, this
is receive address bit 0.
Input
FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 0
In the ATM UTOPIA slave interface supported by FCC1, this
is receive address bit 0.
Description
1-37
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